Abstract: A gate-controlled quantum wire device is disclosed, which may use a channel of electrically resistive material involving tunneling between localized states.

Abstract: A Josephson junction device comprising a single crystalline substrate including a principal surface having two horizontal planes and a smooth slope between the two horizontal planes, and an oxide superconductor thin film formed on the principal surface of the substrate. The oxide superconductor thin film includes a first and a second superconducting portions of a single crystalline oxide superconductor respectively positioned on the two horizontal planes of the substrate, a junction portion of a single crystalline oxide superconductor having a different crystal orientation from the two superconducting portions positioned on the slope of the substrate and two grain boundaries between each of the two superconducting portions and the junction portion. The grain boundaries constitutes one weak link of the Josephson junction.

Abstract: Disclosed is a method of forming an interconnection pattern which causes no disconnection even when making contact with water in the atmosphere. An interconnection layer is formed on a semiconductor substrate. The interconnection layer is selectively etched by employing a halogen-type gas, to form an interconnection pattern. Ultraviolet rays are directed onto the interconnection pattern in the atmosphere including a hydrogen gas. This method avoids generation of hydrogen halogenide which causes corrosion of metal interconnections even when the metal interconnections make contact with water in the atmosphere, thereby to prevent disconnections of the metal interconnections.

Abstract: A semiconductor device having a gold wiring layer for an element region is disclosed, in which the gold wiring layer is connected to the element region through a barrier metal layer, the barrier metal layer comprising first and second layers each containing titanium and a third layer sandwiched between the first and second layers and made of a selected one from platinum and palladium. The third layer effectively prevents gold in the gold wiring layer from diffusing into the element region and the second layer enhances the adhesion between the gold wiring layer and an insulating film.

Abstract: An ohmic electrode is formed on a cBN crystal to form a cBN semiconductor device which is used as a solid electronic element. The cBN semiconductor device may be of an n-type, a p-type or a pn junction type wherein molybdenum is deposited onto an n-type doped region of the cBN crystal or platinum is deposited onto a p-type doped region to thereby form an electrode with ohmic characteristic. The deposition of the molybdenum or the platinum is conducted by using a vapor deposition method followed by heating the attached substance at a temperature of 300.degree. C.-1100.degree. C. in an inactive gas atmosphere. The cBN semiconductor device can be used as a solid electronic element or an optoelectronic element for rectifiers, transistors, light emitting diodes and so on and integrated elements thereof.

Abstract: A nanoporous semiconductor material and fabrication technique for use as thermoelectric elements. Starting precursors are mixed in solution so as to thoroughly dissolve in solution which is then reduced. A second phase may be added in solution to provide nanoinclusions which may be subsequently removed. A nanoporous semiconductor is formed whereby lattice thermal conductivity is greatly reduced, due to enhanced phonon scattering on the order of 10 W/cm.multidot..degree.K. The nanoporous semiconductor material may be used as the n- and p- legs in a Peltier couple utilized for a thermoelectric cooler, a cryogenic cooler, thermoelectric power generator, or a thermoelectric heat pump.

Abstract: First and second high-resistivity compound semiconductor channel layers are formed between an undoped compound semiconductor layer and a doped compound semiconductor layer having an electron affinity smaller than the undoped compound semiconductor layer. The first high-resistivity compound semiconductor channel layer is adjacent to the doped compound semiconductor layer, and has an electron affinity distribution that increases toward the undoped compound semiconductor layer. The second high-resistivity compound semiconductor channel layer is located between the first high-resistivity compound semiconductor channel layer and the undoped compound semiconductor layer, and has an electron affinity distribution that decreases toward the undoped compound semiconductor layer. A gate electrode and cap layers are formed on the doped compound semiconductor layer. Source and drain electrodes are formed on the respective cap layers.

Abstract: There is provided a DRAM memory cell structure. The semiconductor structure includes a semiconductor substrate of a first conductivity type having a main surface, source and drain regions of a second conductivity type formed in the main surface area of the semiconductor substrate, word lines extending in a first plane direction and formed on those portions of the semiconductor substrate which respectively lie between the source and drain regions, capacitors each having one of the source and drain regions as a storage node electrode, and bit lines buried in the semiconductor substrate and electrically connected to the source or drain regions, respectively.

Abstract: An integrated circuit package is disclosed herein including one or more dies, each of which has an array of input/output bond pads, a leadframe which includes an array of electrically conductive leads, and an array of bonding wires, each of which extends along its length between and is connected at its opposite ends to a respective die bond pad and a corresponding lead on the leadframe or a corresponding die bond pad on another die. There is also disclosed a technique for using a bridge arrangement to prevent the bonding wires from contacting the die or dies along the length of each of the wires. In fabricating the package just described, the bridge arrangement is provided as part of either the leadframe or part of a heater block which is a component of the equipment that may be used in manufacturing the integrated circuit package.

Abstract: A semiconductor chip includes a long bus line for transmitting digital signals. The semiconductor chip includes transmission lines for transmitting signals between the bus line and other lines. An impedance regulating element having an impedance, which matches the characteristic impedance of the bus line, is connected to each of the transmission lines.

Abstract: Epitaxial growth of films on single crystal substrates having a lattice mismatch of at least 10% through domain matching is achieved by maintaining na.sub.1 within 5% of ma.sub.2, wherein a.sub.1 is the lattice constant of the substrate, a.sub.2 is the lattice constant of the epitaxial layer and n and m are integers. The epitaxial layer can be TiN and the substrate can be Si or GaAs. For instance, epitaxial TiN films having low resistivity can be provided on (100) silicon and (100) GaAs substrates using a pulsed laser deposition method. The TiN films were characterized using X-ray diffraction (XRD), Rutherford back scattering (RBS), four-point-probe ac resistivity, high resolution transmission electron microscopy (TEM) and scanning electron microscopy (SEM) techniques. Epitaxial relationship was found to be <100> TiN aligned with <100> Si. TiN films showed 10-20% channeling yield. In the plane, four unit cells of TiN match with three unit cells of silicon with less than 4.0% misfit.

Abstract: A solid state imaging device of the present invention includes: a semiconductor substrate of one conductive type; a well layer made of a semiconductor of the other conductive type formed on the semiconductor substrate; a photodetecting portion made of a semiconductor of one conductive type formed in an upper portion of the well layer; a high concentration semiconductor layer made of the other conductive type formed in an upper portion of the photodetecting portion; a first region of one conductive type formed in an upper portion of the semiconductor substrate, being in contact with the well layer and positioned at least below the photodetecting portion, having higher concentration than the semiconductor substrate; and a second region of the other conductive type formed in a lower portion of the well layer, being in contact with the semiconductor substrate and positioned on the first region.

Abstract: An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.

Abstract: An optical semiconductor device having a substrate; a plurality of light-emitting diodes disposed in a specific arrangement on the substrate; a peripheral member for housing the substrate and the light-emitting diodes; a first resin layer formed on an area of said substrate within the peripheral member and not occupied by said light-emitting diodes, for securing the light-emitting diodes between the substrate and the peripheral member; and a second resin layer formed on the first resin layer, wherein: minute irregularities are formed on the second resin layer so that external light directed onto the exposed surface of the second resin layer is diffusedly reflected.

Abstract: A contact between a heavily-doped region in the substrate and metal is made via a hole in a thick oxide layer and a polysilicon layer. The polysilicon layer is first etched to form a hole for establishing a mask for the eventual contact hole. Prior to forming the contact hole, a sidewall spacer of polysilicon is formed in the hole in the polysilicon layer. A thin oxide layer over the polysilicon layer is used for convenient end point detection during the formation of the polysilicon sidewall spacers. The sidewall spacer reduces the bore dimension of the hole in the polysilicon used for the mask for forming the contact hole. A hole is then etched in the thick oxide which is sloped and which has a bore dimension determined by the hole in the polysilicon which is reduced due to the sidewall spacer. The heavily-doped region, the contact hole, and the remaining polysilicon are coated with a barrier. The contact hole is then filled with a conductive material which also coats the barrier.

Abstract: The disclosure relates to a Josephson junction formed by a non-superconducting barrier between two superconducting films of the (R) BaCuO (R=rare earth) group. In order to take advantage of the greater coherence length of superconductors along the CuO planes, i.e. perpendicularly to the long axis "c" of the crystal unit cell, the superconducting film is oriented so that the axis "c" is parallel to the plane of the junction. The device can be applied to Josephson junctions and to SQUIDs.

Abstract: A superconducting switch is composed of anisotropic magnetic material. The switch has a first superconducting section, a variable resistive section and a second superconducting section. An external magnetic field is applied so that the first and second superconducting sections remain superconducting and the resistive section changes resistance when the magnetic field applied exceeds the critical field of the variable resistance section. The different critical field regions are achieved by exploiting the natural critical field anisotropy of the ceramic superconductors (a previously unobserved phenomena in metal superconductors). By making the different sections with different orientations they will exhibit different critical field valves for a given direction of applied fields. The state of the switch is changed by either increasing or decreasing the external magnetic field about the critical field value of the resistive section of the switch.

Abstract: A high current Fermi-FET includes an injector region of the same conductivity type as the Fermi-Tub region and the source and drain regions, located adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate the relatively low doping concentration of the Fermi-Tub and the relatively high doping concentration of the source region. The injector region controls the depth of the carriers injected into the channel and maximizes injection of carriers into the channel at a predetermined depth below the gate. The injector region may also extend to the Fermi-tub depth to decrease bottom leakage current. Alternatively, a bottom leakage current control region may be used to decrease bottom leakage current. Lower pinch-off voltage and increased saturation current are obtained by providing a gate sidewall spacer which extends from adjacent the source injector region to adjacent the sidewall of the polysilicon gate electrode of the Fermi-FET.