Abstract: A method for depositing monocrystalline silicon at a uniform rate onto a plurality of unequally sized monocrystalline nucleation sites comprises initially providing a substrate having an apertured oxide mask on a major surface thereof. The oxide mask includes a plurality of apertures each of which exposes a nucleation site on the substrate surface. The substrate is then exposed to a mixture of dichlorosilane and hydrogen chloride at 850.degree. C. and a pressure less than approximately 50 torr, for a predetermined time. This yields a monocrystalline silicon island extending from each nucleation site. Each of the islands has a substantially flat profile across the major surface thereof and all islands are equal in thickness.

Abstract: Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.

Abstract: A method for the prevention of dopant diffusion from the back side of a doped semiconductor substrate during epitaxial layer growth. The entire surface of the substrate is first covered with a cleanly etchable material. Around the entire first layer is formed a second dopant diffusion barrier layer. The front sides of the layers are then selectively etched away to expose the front side of the substrate upon which the epitaxial layer will be grown without contamination of dopant diffusion from the sealed back side of the substrate.

Abstract: The present invention accomplishes the thermal oxidation of the silicon side of the interface present in epitaxial silicon films grown on yttria-stabilized cubic zirconia, <Si>/<YSZ>, to form a dual-layer structure of <Si>/amorphous SiO.sub.2 /<YSZ>. The SiO.sub.2 films are formed in either dry oxygen (at 1100.degree. C.) or in pyrogenic steam (at 925.degree. C.) by the rapid diffusion of oxidizing species through a 425 .mu.m thick cubic zirconia substrate. For instance, a 0.17 .mu.m thick SiO.sub.2 layer is obtained after 100 min in pyrogenic steam at 925.degree. C. This relatively easy transport of oxidants is unique to YSZ and other insulators which are also superionic oxygen conductors, and cannot be achieved in other existing Si/insulator systems, such as silicon-on-sapphire.

Abstract: A method and apparatus for forming epitaxial thin film layers on substrates having abrupt transitions between layers of different composition or layers of different or like composition with different degrees of doping included therein. Gaseous reactants containing the desired elements to be included in the first film layer are injected into a CVD reaction chamber containing a substrate. The substrate is heated to a temperature high enough to obtain an epitaxial deposit, but low enough so as not to cause decomposition of the reactants. Once the gaseous reactant flows reach steady-state, an electric discharge or plasma is created in the gases to initiate the decomposition reaction and obtain a deposit. In this way, no transient effects are present. Once the deposit has attained sufficient thickness, the electric discharge is turned off to abruptly terminate deposition.

Abstract: In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.

Abstract: Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions.

Abstract: Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the transistor (24) is precisely doped around its edges by ion implanting an epitaxial silicon layer (13) on a sapphire substrate (11), with an oxide mask (29) covering, with the exception of a narrow peripheral edge (37), the portion of the silicon which is eventually to form the island (19') on which the transistor is to be constructed. The mask (29) is then expanded by the addition of a sleeve (43) to cover the additional peripheral edge region (37) in the silicon. When the silicon is subsequently etched using the expanded oxide pattern 45 as a mask, the periphery of the remaining silicon will be doped to a predetermined depth (37) corresponding to the width of the sleeve (43).

Abstract: A method of manufacturing a semiconductor device, in which method a plurality of epitaxial layers are deposited by molecular beam epitaxy. A significant problem in such a method is the variation in the flux emitted by an effusion cell after the shutter associated with that cell has been opened, this resulting in undesired variations in the composition in the thickness direction of the epitaxial layer being grown. In a method according to the invention, when the shutter of a molecular beam source is opened, the rate of input of heat to that source is increased by a predetermined value so that the temperature of that source does not change substantially as a result of the opening of that shutter, and when the shutter is closed the rate of input of heat to that source is reduced by the predetermined value.

Abstract: A method of manufacturing a semiconductor substrate having a modified layer therein comprises the steps of mirror-polishing one surface of each of first and second semiconductor plates, forming a modified layer on at least one of the polished surfaces of the first and second semiconductor plates, and bonding the polished surfaces of the first and second semiconductor plates with each other in a clean atmosphere.

Abstract: There is disclosed a substrate having thereon a layer of a semiconductor material, and a method for depositing and heating the semiconductor material on the substrate, wherein the substrate comprises a layer of organic polymer, a layer of metal or metal alloy, and a layer of dielectric material wherein the layer of dielectric material has a surface, remote from the metal, that is contiguous with the semiconductor material.

Abstract: A method of device fabrication using selective area regrowth Group III-V compound semiconductors with tungsten patterning is described.

Abstract: A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium is overlayed on the die structure covering thereby the pre-patterned polysilicon gates and interconnections. The die is then rapidly heated and baked to form a silicide layer superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.

Abstract: Epitaxial layers of semiconductor materials such as, e.g., III-V and II-VI materials are deposited on a substrate under high-vacuum conditions. Molecules of a compound of a constituent of such material travel essentially line-of-sight towards the substrate admixed to a carrier gas such as, e.g., hydrogen. For III-V layers the use of compounds, such as, e.g., trimethyl- and triethylgallium, trimethyl- and triethylindium, triethylphosphine, and trimethylarsine is advantageous and economical in the manufacture of electronic and opto-electronic devices.

Abstract: A process is disclosed for manufacturing electrically isolated semiconductor device structures. The process includes the steps of providing a semiconductor substrate and selectively etching one surface of that substrate to form etched regions and unetched regions. In a single epitaxial growth step three separate epitaxial layers are grown overlying both the etched and unetched regions. The epitaxial layers are then shaped back to form a substantially planar surface and to expose portions of the first epitaxial layer. The exposed portion of the first epitaxial layer, in combination with the substrate, is suitable for the fabrication of a back contact power transistor. The second epitaxial layer, which follows the contour of the etched surface, bends upwardly and intersects the planar surface to substantially surround portions of the third epitaxial layer and to electrically isolate those portions of the third epitaxial layer from the substrate and first epitaxial layer.

Abstract: A zinc selenide or zinc selenide-sulphide epitaxial crystal is grown at a growth temperature of about 180.degree.-320.degree. C. by organometallic chemical vapor deposition by using zinc alkyl and hydrogen selenide and/or hydrogen sulphide. An as-grown crystal presented an n conductivity type low resistivity and exhibited a narrow near-band gap emission peak. Besides a crystal of the same material as the epitaxial layer, crystals of group III-V, group IV, and so forth having the same or similar crystal structure as the epitaxial layer can be used as an underlayer for the growth.

Abstract: An epitaxially grown high resistivity crystalline layer of gallium arsenide is produced in a reactor vessel with a predetermined amount of carbon dioxide introduced during growth of the high resistivity gallium arsenide (GaAs) crystalline layer to provide carbon as a dopant. Thus, a plurality of carbon atoms is provided in the crystal, such carbon atoms having electrons at energy levels between a valance energy band and a conduction energy band of the GaAs crystal. With these energy levels, the carbon atoms are substantially ionized at room temperature by accepting a plurality of electrons from the valance band of the GaAs. The presence of these carbon ions in the crystal compensates for a stoichiometric defect which occurs during epitaxial growth of the GaAs crystalline layer. This results in a high resistivity layer which provides a buffer layer between a GaAs substrate and an active GaAs layer.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Abstract: Full oxide isolation of epitaxial islands can be accomplished by oxidizing suitably porous silicon. The porous silicon can be created by anodizing highly doped n+ silicon in hydroflouric acid. Lesser doped epitaxial regions will not become porous and will become isolated islands suitable for the fabrication of semiconductor devices.