Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for processing resource, a communication system, and a mobility management network element are provided. The method includes: receiving, by a mobility management network element in a packet switched (PS) network, a Release Request message sent by an access network of the PS network or a Handoff Complete message sent by a circuit switched (CS) network when a user equipment (UE) is handed over from the PS network to the CS network; and processing, by the mobility management network element of the PS network, resources of the UE in the PS network. Thus, the processing of resources of the UE in the PS network is achieved when the UE is handed over from the PS network to the CS network. A communication system and a mobility management network element are also provided.

Abstract: An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPUs), (b) two or more associated memory banks (logically or physically partitioned), (c) a specialized controller, and (d) a local bus providing signal coupling compatible with the PCI industry standards. The controller handles most of the primitive operations to set up and control GPU computation. Thus, the computer's central processing unit (CPU) can be dedicated to other tasks. In this case a few controls (simulation start and stop signals from the CPU and the simulation completion signal back to CPU), GPU programs and input/output data are exchanged between CPU and the expansion card. Moreover, since on every time step of the simulation the results from the previous time step are used but not changed, the results are preferably transferred back to CPU in parallel with the computation.

Abstract: A method and device for handling hybrid automatic repeat request (‘HARQ’) operations during transmission mode changes, the method detecting a transmission mode change; and manipulating an HARQ process buffer based on the detecting. Further, a method and network element for handling hybrid automatic repeat request (‘HARQ’) operations during transmission mode changes, the method checking when a user equipment is in a transmission mode uncertainty window; and blocking communications to the user equipment or utilizing a downlink control information format 1A for communications to the user equipment.

Abstract: According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.

Abstract: The present invention relates to data transmission/reception methods using a polar coding scheme, and devices for supporting same. The method for transmitting data by using polar coding in a wireless access system, according to one embodiment of the present invention, may comprise the steps of deriving Bhattacharyya parameters according to data bits input for finding noise-free channels among equivalent channels; allocating data payloads comprising data bits and cyclic redundancy check (CRC) bits to the found noise-free channels; inputting the data payloads into a polar encoder; and transmitting code bits output by the polar encoder, wherein the CRC bits may be allocated to better noise-free channels, among the noise-free channels indicated by the Bhattacharyya parameters, than the data bits.

Abstract: Systems and methods for a workload optimized server for intelligent algorithm trading platforms. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a control circuit coupled to the plurality of CPUs, the control circuit having a memory configured to store program instructions that, upon execution by the control logic, cause the IHS to: set a first number of enabled cores in a first CPU to operate with a first all-core turbo frequency, and set a second number of enabled cores in a second CPU to operate with a second all-core turbo frequency, where the first number of enabled cores is different from the second number of enabled cores, and where at least one of the first or second all core turbo frequencies is selected to cause the IHS to operate with reduced execution jitter.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

Abstract: Systems and methods for determining available bandwidth and performing initial stream selection when commencing adaptive bitrate streaming using Hypertext Transfer Protocol (HTTP) in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes measuring network bandwidth using a playback device, determining an initial network bandwidth estimate using the network bandwidth measurements, selecting an initial stream from said plurality of streams of encoded media that are encoded at different maximum bitrates rates using the playback device based upon the maximum bitrates of the plurality of streams and the initial bandwidth estimate; and commencing streaming of encoded media by requesting portions of the encoded media from the initial streams using the playback device.

Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.

Abstract: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing. System and method for operating a wireless device to encode data using low-density parity-check (LDPC) encoding is discussed.

Abstract: According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.

Abstract: An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPUs), (b) two or more associated memory banks (logically or physically partitioned), (c) a specialized controller, and (d) a local bus providing signal coupling compatible with the PCI industry standards. The controller handles most of the primitive operations to set up and control GPU computation. Thus, the computer's central processing unit (CPU) can be dedicated to other tasks. In this case a few controls (simulation start and stop signals from the CPU and the simulation completion signal back to CPU), GPU programs and input/output data are exchanged between CPU and the expansion card. Moreover, since on every time step of the simulation the results from the previous time step are used but not changed, the results are preferably transferred back to CPU in parallel with the computation.

Abstract: A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.

Abstract: The present invention relates to data transmission/reception methods using a polar coding scheme, and devices for supporting same. The method for transmitting data by using polar coding in a wireless access system, according to one embodiment of the present invention, may comprise the steps of deriving Bhattacharyya parameters according to data bits input for finding noise-free channels among equivalent channels; allocating data payloads comprising data bits and cyclic redundancy check (CRC) bits to the found noise-free channels; inputting the data payloads into a polar encoder; and transmitting code bits output by the polar encoder, wherein the CRC bits may be allocated to better noise-free channels, among the noise-free channels indicated by the Bhattacharyya parameters, than the data bits.

Abstract: A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

Abstract: A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.