Patents Examined by William Partridge
  • Virtual architectures in a parallel processing environment
    Patent number: 8078832
    Abstract: An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: December 13, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Anant Agarwal, David Wentzlaff
  • Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction
    Patent number: 8055886
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Virtual architectures in a parallel processing environment
    Patent number: 8046563
    Abstract: An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: October 25, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Anant Agarwal, David Wentzlaff