Patents Examined by Wilner Jean Baptiste
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Patent number: 11963383Abstract: A lower part protection film for an OLED panel is provided. More particularly, a lower part protection film for an OLED panel, having a significantly improved recognition rate of an alignment process, being capable of preventing generation of static electricity through an antistatic treatment, and having excellent adhesion to an OLED panel at the same time, and an organic light-emitting display apparatus including the lower part protection film for an OLED panel are provided.Type: GrantFiled: August 20, 2021Date of Patent: April 16, 2024Assignee: Samsung Display Co., Ltd.Inventors: Youngseo Choi, Sangshin Kim, Jinhyuk Kim, Youngdon Park, Youngbin Baek, Sangwoo Lee
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Patent number: 11955461Abstract: Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.Type: GrantFiled: August 24, 2021Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventor: Shiro Uchiyama
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Patent number: 11955391Abstract: Methods and systems for estimating values of process parameters, structural parameters, or both, based on x-ray scatterometry measurements of high aspect ratio semiconductor structures are presented herein. X-ray scatterometry measurements are performed at one or more steps of a fabrication process flow. The measurements are performed quickly and with sufficient accuracy to enable yield improvement of an on-going semiconductor fabrication process flow. Process corrections are determined based on the measured values of parameters of interest and the corrections are communicated to the process tool to change one or more process control parameters of the process tool. In some examples, measurements are performed while the wafer is being processed to control the on-going fabrication process step. In some examples, X-ray scatterometry measurements are performed after a particular process step and process control parameters are updated for processing of future devices.Type: GrantFiled: September 7, 2021Date of Patent: April 9, 2024Assignee: KLA-Tencor CorporationInventors: Antonio Arion Gellineau, Thaddeus Gerard Dziura
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Patent number: 11948909Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.Type: GrantFiled: January 12, 2022Date of Patent: April 2, 2024Assignee: QUALCOMM INCORPORATEDInventors: Yangyang Sun, Dongming He, Lily Zhao
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Patent number: 11948857Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first pad above the substrate, forming a first redistribution conductive layer on the first pad, and forming a first redistribution thermal release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm2/Watt and about 0.25° C. cm2/Watt.Type: GrantFiled: March 3, 2022Date of Patent: April 2, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Jar-Ming Ho
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Patent number: 11948906Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.Type: GrantFiled: February 7, 2020Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Feras Eid, Joe Walczyk, Weihua Tang, Akhilesh Rallabandi, Marco Aurelio Cartas Ayala
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Patent number: 11942336Abstract: An underfill film for semiconductor packages and a method for manufacturing a semiconductor package using the underfill film are disclosed. The underfill film includes an adhesive layer in which a melt viscosity and an onset temperature are adjusted to a predetermined range such that production efficiency may be improved by simplifying packaging process of the semiconductor packages. Also the underfill film and the manufacturing process may improve connection reliability of the package.Type: GrantFiled: August 17, 2021Date of Patent: March 26, 2024Assignee: DOOSAN CORPORATIONInventors: Taejin Choi, Chunggu Lee, Sooin Park, Jungjin Lee
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Patent number: 11942447Abstract: The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.Type: GrantFiled: August 27, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Yang Chiou, Fu-Ting Yen, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 11942445Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.Type: GrantFiled: August 23, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-En Yen, Chin-Wei Kang, Kai-Jun Zhan, Wen-Hsiung Lu, Cheng-Jen Lin, Ming-Da Cheng, Mirng-Ji Lii
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Patent number: 11935871Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.Type: GrantFiled: August 30, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
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Patent number: 11937429Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.Type: GrantFiled: December 20, 2021Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
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Patent number: 11935850Abstract: The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.Type: GrantFiled: November 30, 2021Date of Patent: March 19, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Kuo-Hui Su
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Patent number: 11923257Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.Type: GrantFiled: August 19, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard Christopher Stamey, Amruthavalli Pallavi Alur
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Patent number: 11923256Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.Type: GrantFiled: July 16, 2021Date of Patent: March 5, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventors: Olivier Franiatte, Richard Rembert
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Patent number: 11916030Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.Type: GrantFiled: April 22, 2022Date of Patent: February 27, 2024Assignee: PANJIT INTERNATIONAL INC.Inventors: Chung-Hsiung Ho, Chi-Hsueh Li
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Patent number: 11908816Abstract: The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.Type: GrantFiled: November 30, 2021Date of Patent: February 20, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11894327Abstract: Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.Type: GrantFiled: August 18, 2021Date of Patent: February 6, 2024Assignee: Micron Technology, Inc.Inventors: Wei Zhou, Chien Wen Huang
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Patent number: 11894247Abstract: The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.Type: GrantFiled: November 5, 2021Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Hsih-Yang Chiu
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Patent number: 11894284Abstract: A semiconductor structure having a silver-indium transient liquid phase bonding joint is provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.Type: GrantFiled: November 24, 2021Date of Patent: February 6, 2024Assignee: LMDJ MANAGEMENT LLCInventors: Yongjun Huo, Chin Chung Lee
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Patent number: 11887948Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.Type: GrantFiled: August 2, 2021Date of Patent: January 30, 2024Assignee: STMicroelectronics S.r.l.Inventors: Simone Dario Mariani, Elisabetta Pizzi, Daria Doria