Abstract: Techniques for managing memory buffers include maintaining a pool of buffers and assigning the buffers to buffer classes based on the frequency with which information stored in the buffers is accessed. Different algorithms can be used to manage buffers assigned to the different classes. A determination can be made as to whether a particular buffer qualifies for entry into a particular one of the buffer classes based on a comparison between a threshold value and the frequency with which information stored in the particular buffer was accessed during a specified time interval. Additionally, the threshold value can be adjusted dynamically to take account, for example, of the current load on the system.

Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.

Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. In conventional systems using a MESI approach, two or more processors will often compete for ownership of a common cache line. As a result, ownership of the cache line will frequently “bounce” between multiple processors, which causes a significant reduction in cache efficiency. The preferred embodiment provides a modified MESI state which holds the status of the cache line static for a fixed period of time, which eliminates the bounce effect from contention between multiple processors.

Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.

Abstract: A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage unit. The storage control apparatus has at least two processors coupled to the CPU and the storage unit, a cache memory (CM) unit for temporarily storing data of the storage unit, a shared memory (SM) unit for storing information concerning control of the CM unit and the storage unit, and a selector coupled to the at least two processors, the CM unit and the SM unit through access paths to selectively apply access requests from the at least two processors to the CM unit and the SM unit.

Abstract: A memory access request handling unit is arranged between a source of memory access requests and a data storage element that is the target of the memory access requests. The memory access request handling unit comprises a queue made up of a number of queue elements, each being capable of temporarily storing one memory access request. Comparison logic is arranged to monitor a window of the queue and to select one or more of the queue elements, representing memory access requests not yet transmitted to the data storage element, for transmission to the data storage element. The selection is made on the basis of a comparison between the memory access requests held in the queue and one or both of a priority value set for each memory access request and a list of memory access requests that are currently pending at the data storage element, the list being maintained in a list store of the memory access request handling unit.

Abstract: A system and method for optimally processing split request transactions across a PCI-X bridge with a PCI-X bridge buffer. The split transaction mode of the PCI-X bridge buffer is toggled between a No Over-commit mode and an over-commit mode. Over-commitment of the buffer is inhibited when the split transaction mode is toggled to the No Over-commit mode and when the buffer is over committed by the bridge. At least some over-commitment of the buffer is allowed by the bridge when the split transaction mode is toggled to the over-commit mode and when the buffer is not over committed by the bridge. The over-commit mode may be an Over-commitment mode or a Flood mode. The Over-commitment mode allows some degree of over commitment of the buffer by the bridge while the Flood mode allows the bridge to forward all split request transactions regardless of size of the transactions or amount of available space in the buffer when the Over-commit mode is in a Flood mode.

Abstract: A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.

Abstract: A data processing apparatus for handling multi-thread programs comprises a data processor coupled with a random-access memory containing a plurality of data objects. Each data object is accessed via respective pointers carried by memory stacks associated with respective threads. Periodically, a garbage collection procedure is applied to the random-access memory with those data objects having no extant pointers thereto from any source being identified and deleted. Subject to a locking constraint applied to some of the data objects, the remainder are compacted to free space in the memory. To enable localising of the garbage collection procedure, reference stacks are provided for each thread stack frame such as to identify, preferably via a per-thread reference table, data objects referenced from only a single frame, which objects are deleted on conclusion of that frame.

Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an additional cache state which specifically indicates that a processor has released its lock on a cache line after it has performed any necessary modifications.

Abstract: Memory allocator combines private (per thread) sets of fixed-size free blocks lists, a global, common for all threads, set of fixed-sized free block lists, and a general-purpose external coalescing allocator. Blocks of size bigger than the maximal fixed size are managed directly by the external allocator. The lengths of fixed-size lists are changed dynamically in accordance with the allocation and disallocation workload. A service thread performs updates of all the lists and collects memory associated with terminated user threads. A mutex-free serialization method, utilizing thread suspension, is used in the process.

Abstract: Apparatus for processing memory access requests includes first and second state machines for controlling access to first and second memory banks and an arbiter. While the first state machine is processing a current memory access request for the first memory bank, the arbiter recieves a next memory access and determines wheather the next memory access request will interfere with the processing of the current memory access request. If no interference will occur, and if the next access request is directed to the second memory bank, the second state machine begins processing he next memory access request before completion of processing of the current memory access request. The second state machine begins processing of the next memory access request during a mandatory wait period implemented by the first state machine. The first and second state machines process the current and next memory access request concurrently.

Abstract: In a data processing network including a plurality of array controllers connected for communication to each other and a plurality of data storage devices, a method for coordinating exclusive write access by the plurality of controllers to a shared data region on said plurality of data storage devices comprising the steps of: at a first array controller, broadcasting an exclusive access request to all other array controllers having access to the shared data region and storing a non-volatile record of the write operation in the first controller; and at each controller receiving the exclusive access request, storing a non-volatile record of the write operation prior to sending an exclusive access grant to the first controller.

Abstract: A method and computer program for allocating storage for a header and one or more data elements in a data storage facility are disclosed. The method and computer program include computing a hole size B that is a portion of a word that would be unallocated if storage were allocated to the header and to the data elements in a preferred order. The method and computer program include finding a subset of data elements S={Fi1, Fi2, . . . , Fin} that satisfy the equation (SizeModN(Fi1)+SizeModN(Fi2)+ . . . +SizeModN(Fin))mod N=B where N is the largest alignment requirement associated with any data element. The method and computer program include allocating storage to data elements in S first and allocating storage to the remaining elements in the preferred order. A lookup table and a method for building the lookup table are also disclosed.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.

Abstract: The present invention relates to a system and method for inserting one or more files onto a mass storage device during a boot sequence. The method includes loading a content module containing at least one file into memory. The method further includes replacing a target module that is typically executed during a boot sequence with a utility module. The method also includes executing the utility module during the boot sequence to move the content module onto a mass storage device.

Abstract: The invention enables reduction of latency time for receipt of data which has been requested from a disk system. The method enables use of a read command which enables a cache memory output to occur only when the read command has been completed. The method of the invention initially receives a read request from a host processor for a number of data blocks on a disk track (referred to as requested blocks), the requested blocks being a subset of blocks stored in the disk track. If the requested blocks are not already stored in a cache memory, the method constructs at least a first command to transfer the track to cache memory, the first command enabling identification of a last data block of the requested blocks. A second command is also prepared to transfer the track to cache memory, the second command enabling identification of the last block of the remaining set of blocks in the track.

Abstract: One embodiment of the present invention provides a system that enforces dependencies between memory references within a load store unit (LSU) in a processor. When a write request is received in the load store unit, the write request is loaded into a store buffer in the LSU. The write request may include a “watch address” specifying that a subsequent load from the watch address cannot occur before the write request completes. Note that the watch address is not necessarily the same as the destination address of the write operation. When a read request is received in the load store unit, the read request is loaded into a load buffer of the LSU. The system determines if the read request is directed to the same address as a matching watch address in the store buffer. If so, the system waits for the write request associated with the matching watch address to complete before completing the read request.