Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.

Abstract: A method for fabricating a y-direction, self-alignment mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a gate oxide layer on the substrate. Perpendicular to the direction of the buried drain region, a bar-shaped silicon nitride layer is formed on the gate oxide layer. A photoresist layer is then formed on the gate oxide layer and the bar-shaped silicon nitride layer. Performing a code implantation to form a plurality of coded memory cells using the photoresist layer as a mask. The photoresist layer is then removed. A polysilicon layer is further formed on the gate oxide layer and the bar-shaped silicon nitride layer. The polysilicon layer is back-etched until the bar-shaped silicon nitride layer is exposed. The silicon nitride layer is subsequently removed.

Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects. Another method includes epitaxially growing a layer of group III-nitride semiconductor on a lattice-mismatched crystalline substrate and then, chemically treating a growth surface of the layer to selectively electrically passivate defects that thread the layer.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of the polysilicon residue. An oxygen anneal step is subsequently performed to completely convert the rich oxygen containing polysilicon residue into silicon dioxide that can eliminate the conductivity of the polysilicon residue and prevent oxygen encroachment occurring.

Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013 ˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TPT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.

Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer over top surfaces and sidewalls of the portion of the first conducting layer and the portion of the sacrificial layer, and f) partially removing the second conducting layer while retaining a portion of the second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, and removing the portion of the sacrificial layer to expose the etching stop layer and construct a capacitor plate with a generally crosssectionally modified T-

Abstract: A continuous barrier layer is formed after a local interconnect metal layer is formed between the top electrode of a ferroelectric capacitor and the source/drain contact of a memory cell transistor in an integrated ferroelectric memory. After contact has been made to the top electrode of the ferroelectric capacitor, a thin dielectric layer is deposited using a material that provides an effective hydrogen barrier to the ferroelectric capacitor. The barrier layer minimizes damage to the ferroelectric capacitor and thus improves electrical performance.