Abstract: System, method and computer product for performing automated predictive reliability. A data acquisition component acquires service data for a complex system from a data repository. A statistical analysis component generates a statistical model for the service data. A simulation component predicts the reliability of the complex system according to the statistical model. An alert generation component generates alerts when predicted failures determined by the simulation component exceed predetermined alert criteria. A report generation component generates a summary of the analysis performed in the data acquisition, statistical analysis and alert generation components.

Abstract: A technique is described for guaranteeing recovery in a computer system comprising of recovery contracts with a plurality of obligations for a message exchange between a first component and a second component. Three forms of contract are described, governing interactions between three types of components. Each contract is bilateral, i.e. between a first component and a second component. The first and second components have mutual agreement on when the contract will be released to facilitate log truncation, and independent and/or autonomous recovery.

Abstract: A system with capabilities for recovering from memory errors includes memory and a processor in communication with the memory. The system also includes an operating system and a BIOS which reside in the memory and are executable by the processor. The BIOS includes recovery logic that detects a memory error in a section of the memory and, in response, instructs the operating system to discontinue use of the section of memory with the memory error. For instance, the system may include multiple memory objects that represent respective sections of the memory. The recovery logic may instruct the operating system to discontinue use of the section of memory with the memory error by sending an eject event to the operating system.

Abstract: A computer managing system includes an active system computer having a heart beat transmission processing unit for transmitting a heart beat signal indicating that an active system computer is being operated in normal to a spare system computer, and transmitting the heart beat signal to a first control unit; a spare system computer including a monitor request processing unit for transmitting a monitoring request of the active system computer to the first control unit in accordance with a determination result of whether or not a fault has occurred in the active system computer; and the first control unit including a heart beat transmit instruction processing unit for instructing a transmission of the heart beat signal to the first control unit, to the active system computer, when receiving the monitoring request from the spare system computer.

Abstract: A system and method for enabling failover in an application server cluster. A “primary” application server computer in the cluster may provide a service or data necessary for other application server computers in the cluster to operate. In addition to the primary application server computer, one or more of the other application server computers may be designated as “backup” application server computers. Each backup application server may backup the processing information managed by the primary application server. When the primary application server itself becomes unavailable (e.g., due to a failure of the computer system or network), one or more of the backup application servers may be promoted to the role of primary application server.

Abstract: A system and method for optimizing fault tolerant storage controllers includes a fault tolerant hardware component comprised of an input interface, at least two output interfaces and, if necessary, a power source connection. The fault tolerant hardware component may be embedded in a storage controller or separately housed within an enclosure. The fault tolerant hardware component may couple with a host information handling system and with two or more storage controllers, which are connected to mass storage devices to form storage arrays. Multiple fault tolerant hardware components can be coupled with a single host information handling system when it includes multiple host ports. Further, the fault tolerant hardware component may be coupled with other fault tolerant hardware components.

Abstract: Method and apparatus for managing memory of a data processing system. In one embodiment, memory objects are allocated in response to memory allocation requests. Each object has an associated plurality of addresses. Type-identifier codes are respectively stored in association with the memory objects. Upon detection of a transient memory error at a memory address a recovery action is selected and performed based on the type-identifier code of the object that is associated with the erring memory address.

Abstract: Parameter values of an emulation parameter that is indicative of a data processing operation performed by a data processor are exported from the data processor. In response to detection of a condition wherein a first portion of a first parameter value is identical to a corresponding portion of a second parameter value, the second parameter value and only a remainder portion of the first parameter value other than the first portion are output from the data processor.

Abstract: A computing node configured for communications on an InfiniBand™ network includes at least two host channel adapters configured for communications on the InfiniBand™ network, and at least one processor configured for controlling the communications of the two host channel adapters on the InfiniBand™ network. The host channel adapters communicate with the processor via an internal bus. The processor monitors communication operations by the host channel adapters on the InfiniBand™ network. If the processor detects that one of the host channel adapters is unable to complete the corresponding communication operations, the processor outputs a message requesting traffic destined to the one host channel adapter to be redirected to the remaining host channel adapter.

Abstract: System for providing distributed group-based protection switching at a network element in a communication network. The communication network includes a plurality of interconnected network elements, and wherein the network element includes first and second card logic coupled to the communication network to transmit and receive network traffic. The system comprises selector logic distributed between the first and second card logic that includes first and second switching engines that have associated activity states that indicate how the network traffic is routed at the network element. The switching engines generate new activity states based on selected fault indicators. A processing system operates to detect fault conditions, generate the selected fault indicators, and receive the new activity states from the switching engines to perform one or more switch reconfigurations at the network element based on the new activity states, and thereby implement the distributed group-based protection switching.

Abstract: A method for displaying variable values within a software debugger is disclosed. A group of variables is extracted from a program monitored by a software debugger. A user is allowed to designate a stopping point, such as a breakpoint, within the program and a subset of variables from the group of variables to be associated with the designated stopping point. During an execution of the program within the software debugger, only the values of the subset of variables are updated when the program execution stopped at the designated stopping point. The updated values of the subset of variables are then displayed on a monitor window of the software debugger.

Abstract: An enduser diagnostic system or “system” (10) for computer-based error interpretation includes a network addressable device (33), a computer-based system (20), and an inspector (40). The network addressable device (33) provides solutions for error problems associated with the computer-based system (20). The computer-based system (20) includes a system registry (26) for storing information required for configuring software and hardware components that define the computer-based system (20). The inspector (40) is a software component linked with the system registry (26) and the network addressable device (33). The inspector (40) compiles examination data by accessing the computer-based system (20) including the system registry (26). By generating examination data, the inspector (40) quickly and accurately provides information, including real-time information, required for assisting the network addressable device (33) with supplying a solution to the error.

Abstract: A method of performing a service which remotely monitors a Web site includes the steps of monitoring the site for an error and notifying a site representative in the event an error is detected on the site. Advance permission is not obtained prior to sending the notification and a fee is not charged for the service. The appropriate e-mail address to which the notification is sent is identified based on one or more categories and a priority assigned to all e-mail addresses identified on the monitored site. The notification may be sent, alternatively, to the representative of a site linked to the site monitored or to some other interested third party. Subscribers to the monitoring service may be enrolled automatically upon submission of their site to a search engine service or to a domain name registry. The list of service recipients generated by the monitoring service is usable for other commercial purposes.

Abstract: A problem detection system detects problems related with operation of a computer system, its hardware components, application programs, and databases. The problem detection system begins by gathering or discovering initial data from one or more of the hardware components, application programs, and databases. The problem detection system may then update this data over time. The problem detection system includes mechanism for discovering problems in the computer system. The problem detection system also includes mechanisms for reporting problems to a user of the computer system or to a system administrator. The problem detection system may report the problems to other components of the computer system, may store data related to the problems, and may present the problem information to the user through a separate display.

Abstract: This invention relates to a method for reconfiguring a network of parallel functional elements tolerant to the faults of these functional elements including said basic functional elements (P), spare functional elements (Sp), interconnecting elements (Cm) of these functional elements and a control unit, said method comprising: a step of positioning the functional elements of the logic network on the physical network; a routing step of programming interconnecting elements on the physical network, by choosing a maximum number of interconnecting elements which can be passed between two neighbouring processors using a shortest track search algorithm.

Abstract: A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.

Abstract: A watchdog monitor coupled to a device bus includes in at least one executable software the ability to produce, during each frame interval, a strobe addressing a predetermined number to the monitor. The monitor responds to the interrupt and to lack of arrival of the correct predetermined number by generating a fault flag. The monitor also runs an internal counter which is reset at each interrupt signal; the count of the internal counter exceeds a threshold count if an interrupt fails to arrive. Such a timed failure results in setting of a frame fault flag. The monitor further runs an internal clock independent of the system clock. A further missing pulse detector initiates a counter at each monitor clock pulse, and raises a flag if the monitor clock counter counts a duration exceeding the monitor inter-clock-pulse interval.

Abstract: An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.

Abstract: The present invention provides a system, apparatus, and method for managing a data storage system in n-way active controller configuration, such that a controller can detect the failure of and reset more than just a single other controller. To accomplish this, a controller sends a ping message to at least a subset of the other controllers, and waits for any of the other controllers to respond to the ping message within a first predetermined amount of time. If any of the other controllers do not respond to the ping message within the first predetermined amount of time, it is determined that the non-responding controller has failed. The controller will reset any failed controller.

Abstract: A method and apparatus for efficiently testing input/output (I/O) buffer are disclosed. The I/O buffer includes multiple transistors coupled to a data output terminal. The method includes enabling a single one of the multiple transistors. A predetermined electrical voltage level is then forced upon the data output terminal, and a resultant electrical current flowing through the data output terminal (e.g., in a direction away from the I/O buffer) is measured. The measured electrical current is compared to predetermined minimum and maximum current values. A ratio of the measured electrical current to a reference current is computed, and the computed current ratio is compared to a predetermined minimum and maximum current ratio. The above steps may be repeated until each of the multiple transistors has been enabled. The drive strength of a given transistor is a measure of the amount of electrical current the transistor causes to flow through the data output terminal when enabled.