Abstract: A decision error correcting method that is adopted to a general digital communication system having a decision circuit finding an original message from a received signal to remove a misdecision-to-adjacent symbol. The decision error correcting method includes performing a soft decision for a received suspicious signal with all the candidate symbols, computing error distances between the suspicious signal and all the candidate symbols, computing respective error distances between each candidate symbol and following signals received immediately after the suspicious signal for a predetermined test period of time, adding the error distances for each candidate symbol, comparing sums of the error distances to select a least sum of the error distances, and selecting the candidate symbol and following symbols detected after the selected candidate symbol resulting in the least sum of the error distances as original message symbols corresponding to one suspicious signal and the following signals.

Abstract: A CD-ROM decoder provides error correction for header data of digital data read out from a ROM disc. Address information contained in the header data of the read out digital data is stored in an address information register 31. An adder 32 adds a value "1" to a value of the address information stored in the register 31. The added value is stored in the final address information register 33 at timing delayed by one frame. A comparison circuit 35 compares the two data stored in the registers 31 and 32, respectively, and detects an error based on lack of coincidence between the two data values. When an error is detected, a selection circuit 34 selects and output address data stored in the final address information register 33.

Abstract: A microcontroller capable of operating in any one of several operation modes and includes first latch circuits which latch first mode signals from first external nodes at a first timing and second latch circuits latching second mode signals from the same external nodes at a second timing. Operation modes are switched by using the mode signals stored in the first and second latch circuits, so that a single external node can provide two bits for expressing the operation modes. Thus, the number of bits used to represent the mode signal can be increased without increasing the number of external nodes. Also provided is a microcontroller in which the time required for a test can be reduced by eliminating the waiting period for clock generation to be stabilized.

Abstract: A polynomial divider which can perform Euclid's Algorithm by iteratively solving both equations thereof through performing iterations of polynomial division so as to produce an error locator polynomial from an error syndrome polynomial, and apparatus including the polynomial divider. The polynomial divider is capable of performing polynomial division of a numerator polynomial by a denominator polynomial to produce a quotient polynomial and a remainder polynomial.

Abstract: Semi-Automatic Number Verification (SNV) on an electronic adding machine employing a small amount of random access memory (RAM), a microprocessor, a printer link and printer, a piezo-electric speaker to facilitate conventional adding machine capabilities with the additional SNV feature employing an enable/disable (SNV) button. A keypunch operator depresses the SNV key to start the SNV process entering numbers with either the plus (+) or minus (-) key, entered appropriately into the RAM, and particularly an RAM module including first and second series arrays and first and second counters. When the operator depresses the TOTAL key, the printer is enabled, if it is currently switched on. The operator then enters the second series of numbers and the microprocessor compares the values to those stored in the RAM module. If a discrepancy is detected, the adding machine enters an edit mode in which the operator need only look at the original source document and the display for verification of entries.

Abstract: When new data for writing is sent from a host device, old data and old parities are read after a search time respectively, and a new parity is generated with the new data, the old data and the old parities, and the new parity is stored in a cache memory, and when the number of the new parities corresponding to a plurality of write data becomes more than a predetermined value set by a user or when there is a period of time in which no read request or no write request is issued, new parities are collectively written to a drive for storing parities. In this case, a plurality of new parities are written in a series of storing positions, where a plurality of old parities are stored, in a predetermined access order independent of the stored positions of corresponding old parities. At least to a plurality of storing positions in a track, these new parities are written in the order of positions in a track.

Abstract: A control device for use in a sewing machine and a control method in which the memory contents of a memory element are read when a servo microcomputer generates an interrupt. The control device also changes sewing data by specifying a rewriting format when sewing data are changed, automatically detects the rewriting of the memory contents of a rewritable memory element due to noise, and restores the memory contents to their original state before they have actually been rewritten.

Abstract: A process control system having a feedback controller, at least one manipulated variable and one controlled variable with a feedforward loop is provided. Independent feedforward control is incorporated into the feedback controller by defining a feedforward control funnel and a feedback control funnel for each controlled variable, specifying a time T.sub.FF in which the disturbance is to be eliminated and a time T.sub.FB in which the controlled variable is to reach a steady state value, respectively. The shorter of the feedforward control funnel and the feedback control funnel is selected. If T.sub.FF is less than T.sub.FB, the feedback control speed is compensated such that the feedback controller speed is not increased. If T.sub.FF is greater then or equal to T.sub.FB, no compensation is performed, thereby effectively providing independent tuning parameters for the feedforward control solution and the feedback control solution.