Patents Examined by Yoncha L. Kundupoglu
  • Patent number: 5574735
    Abstract: In an error correction circuit, when a data loss is detected, substitute data comprising all bits of "1" or "0" are generated during a data loss period and substituted for the lost data for the data loss period. Thereafter, the whole data containing the substitute data are decoded in a predetermined error correction system to generate corrected data.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: November 12, 1996
    Assignees: Nippon Hoso Kyokai, Nippon Conlux Co., Ltd.
    Inventors: Masayuki Takada, Osamu Yamada, Toru Kuroda, Koichi Yamazaki
  • Patent number: 5563897
    Abstract: The transmitted bits are coded according to the product of at least two systematic block codes. An iterative decoding is applied in order to determine, at each code word search step, a data matrix and a decision matrix which are used for the following step. The new decision matrix is determined at each step by decoding the rows or the columns of the input matrix, and the new data matrix is determined by taking account of correction terms which increase the reliability of the decoding at each iteration. The method is especially suited for use with high-efficiency block codes.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: October 8, 1996
    Assignee: France Telecom
    Inventors: Ramesh Pyndiah, Alain Glavieux, Claude Berrou