Abstract: A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.

Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.

Abstract: Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap. The gate structure is disposed over the semiconductor substrate. The first gate spacer covers a first sidewall of the gate structure. The interlayer dielectric layer is adjacent to the first gate spacer. The contact stop layer is positioned over the first gate spacer and the interlayer dielectric layer. The air gap is between the first gate spacer and the interlayer dielectric layer. The contact stop layer includes a capping portion that seals a top of the air gap.

Abstract: A micro-transfer printed intermediate structure comprises an intermediate substrate and one or more pixel structures disposed on the intermediate substrate. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure. A fractured intermediate tether is physically attached to the intermediate substrate. A method of making an intermediate structure source wafer comprises providing a source wafer having a patterned sacrificial layer including sacrificial portions separated by anchors, disposing an intermediate substrate over the patterned sacrificial layer, and disposing one or more pixel structures on the intermediate substrate entirely on or over each sacrificial portion. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure to form an intermediate structure.

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Abstract: An RC-IGBT includes a semiconductor body incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process and the field stop zone has an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In alternate embodiments, RC-IGBT device, including the epitaxial layer field stop zone, are realized through a fabrication process that uses front side processing only to form the backside contact regions and the front side device region. The fabrication method forms an RC-IGBT device using front side processing to form the backside contact regions and then using wafer bonding process to flip the semiconductor structure onto a carrier wafer so that front side processing is used again to form the device region.

Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.

Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a surrounding part surrounding the semiconductor structure and exposing a surface of the first semiconductor layer; a first insulating structure formed on the semiconductor structure, including a plurality of protrusions covering the surface of the first semiconductor layer and a plurality of recesses exposing the surface of the first semiconductor layer; a first contact portion formed on the surrounding part and contacting the surface of the first semiconductor layer by the plurality of recesses; a first pad formed on the semiconductor structure; and a second pad formed on the semiconductor structure.

Abstract: Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.

Abstract: A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.

Abstract: A magnetic memory device includes a substrate, a tunnel barrier pattern on the substrate, a first magnetic pattern and a second magnetic pattern spaced apart from each other with the tunnel barrier pattern therebetween, and a short preventing pattern spaced apart from the tunnel barrier pattern with the second magnetic pattern therebetween. The short preventing pattern includes at least two oxide layers and at least two metal layers, which are alternately stacked.

Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor apparatus and manufacturing methods for the same.

Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Abstract: Embodiments are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device on a substrate. The fabrication operations include, forming a channel stack over the substrate, wherein the channel stack include stacked and spaced apart channel nanosheets. A metal gate is formed adjacent to end regions of the channel stack and around and between the stacked and spaced apart channel nanosheets. A permanent dummy gate is formed above the channel stack.