Abstract: Embodiments relate to a neural engine circuit that includes an input buffer circuit, a kernel extract circuit, and a multiply-accumulator (MAC) circuit. The MAC circuit receives input data from the input buffer circuit and a kernel coefficient from the kernel extract circuit. The MAC circuit contains several multiply-add (MAD) circuits and accumulators used to perform neural networking operations on the received input data and kernel coefficients. MAD circuits are configured to support fixed-point precision (e.g., INT8) and floating-point precision (FP16) of operands. In floating-point mode, each MAD circuit multiplies the integer bits of input data and kernel coefficients and adds their exponent bits to determine a binary point for alignment. In fixed-point mode, input data and kernel coefficients are multiplied. In both operation modes, the output data is stored in an accumulator, and may be sent back as accumulated values for further multiply-add operations in subsequent processing cycles.

Abstract: A system and method which allows the basic checkpoint-reverse-mode AD strategy (of recursively decomposing the computation to reduce storage requirements of reverse-mode AD) to be applied to arbitrary programs: not just programs consisting of loops, but programs with arbitrarily complex control flow. The method comprises (a) transforming the program into a formalism that allows convenient manipulation by formal tools, and (b) introducing a set of operators to allow computations to be decomposed by running them for a given period of time then pausing them, while treating the paused program as a value subject to manipulation.

Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.

Abstract: Devices and techniques for variable pipeline length in a barrel-multithreaded processor are described herein. A completion time for an instruction can be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time can be detected. Here, the different instruction is already in the pipeline and the conflict detected when the completion time equals the previously determined completion time for the different instruction. A difference between the completion time and an unconflicted completion time can then be calculated and completion of the instruction delayed by the difference.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply values of zero are described.

Abstract: According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

Abstract: An artificial intelligence system can be implemented to identify relationships through the propagation of ripple patterns through a grid. In such a system, the grid may comprise cells which operate as cellular automata. Relationships may be identified based on collisions of signals detected by the cells in the grid, and, when a relationship is identified, it may be used to create high speed connections between cells.

Abstract: A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. The tiles can be arranged in an array or grid and can be communicatively coupled. In an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. Each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. The passthrough bus can extend through intervening tiles.

Abstract: A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching instructions if the resources are available based on data stored in the time-resource matrix, and wherein execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline.

Abstract: A processor includes a time counter and a register scoreboard and operates to statically dispatch instructions with preset execution times based on a write time of a register in the register scoreboard and a time count of the time counter provided to an execution pipeline.

Abstract: The disclosure provides a method for scheduling an out-of-order queue The method includes: adding a highest bit before each address in a reorder buffer (ROB) or in a branch reorder buffer (B-ROB), in which the addresses are entered by instructions in the out-of-order queue; adding a highest bit for a read pointer (roqhead) of the ROB or B-ROB; performing an exclusive-OR (XOR) operation on the highest bit for the roqhead and the highest bit for each of the addresses entered by two instructions to be compared, and determining addresses after the XOR operation as age information of the two instructions; and comparing the age information to determine the oldest instruction in the queue for execution in response to scheduling the out-of-order queue.

Abstract: A processor includes a time counter and provides a method for statically dispatching instructions with preset execution times based on a time count from the time counter provided to an execution pipeline.

Abstract: In an embodiment, a processor supports one or more compression assist instructions which may be employed in compression software to improve the performance of the processor when performing compression/decompression. That is, the compression/decompression task may be performed more rapidly and consume less power when the compression assist instructions are employed then when they are not. In some cases, the cost of a more effective, more complex compression algorithm may be reduced to the cost of a less effective, less complex compression algorithm.

Abstract: In an accelerator control system (100), a general-purpose server (110) includes a digest information generation unit (1112) that binarizes an accelerator function to generate first digest information (130) of the accelerator function and a server management control unit (1111) that compares the first digest information (130) created before the accelerator function is implemented on an FPGA function unit (122) with second digest information (130) notified from an accelerator board (120) and determines whether the accelerator function is rewritten, and the accelerator board (120) includes a digest information generation unit (1212) that generates the second digest information (130) of the accelerator function written in the FPGA function unit (122), and an FPGA management control unit (1211) that notifies the general-purpose server (110) serving as a rewriting source of the second digest information (130) generated.

Abstract: Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.

Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.

Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

Abstract: A serial interrupt method includes receiving a blank serial interrupt request signal (SerIRQ) and a level signal of a peripheral, based on the blank SerIRQ, generating an indication SerIRQ including an indication interrupt bit (IRQ_n) according to the level signal, and sending the instruction SerIRQ to a processor. The indication IRQ_n identifies the peripheral based on a binary code represented by a first level and a second level.

Abstract: A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.

Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities.