Abstract: The amount of unsolicited bulk e-mail messages received by an e-mail user is reduced by providing the user with a temporary e-mail address and a permanent e-mail address. The temporary addresses are generated by a server on an ongoing basis. The current temporary address is linked to the permanent e-mail address such that e-mail messages sent to the current temporary address are forwarded to the permanent address and e-mail messages sent to a former temporary address are not forwarded to the permanent address and not received by the user. The method and system also provide a degree of anonymity to the e-mail user.

Abstract: A wireless interface device is adapted to be connected to a host computer. On power-up, a list of available hosts is identified in a dialog box on the display of the wireless interface device. Once a host is selected, the node address for the selected host is stored in an EEPROM. On a subsequent power-up of the wireless interface device, a connection is automatically made to the last selected host.

Abstract: A processing system and method of operation are provided. A particular instruction is dispatched to execution circuitry for execution. After dispatching the particular instruction, an execution serialized instruction is dispatched to the execution circuitry prior to finishing execution of the particular instruction.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A method for controlling the execution of a microprocessor to cause it to execute a NOP instruction for a programmable number of sequential cycles. A NOP instruction is provided, that includes a predetermined OP code field identifying the NOP instruction as a programmably multiple NOP instruction. A predetermined count field is provided, representing the number of sequential cycles in which a NOP operation is to be performed by said microprocessor. The NOP instruction OP code field is read, as is the NOP instruction count field. In response thereto, a NOP operation is performed for the number of sequential cycles represented by said NOP instruction count field.

Abstract: A remote request system and method monitors and controls the execution of remote requests on an on-line services network. When a remotely located client sends a remote request to the on-line service network, the remote request system monitors the remote request while returning operating control back to the client while the remote request remains pending in the on-line service network. The remote request system also provides for the concurrent execution of multiple pending remote requests, provides status information about each remote request, provides for the cancellation of a pending remote request and optimizes the use of memory. In addition, the remote request system dynamically allocates memory when data blocks of unknown size are transmitted over the on-line services network.

Abstract: A computer network includes a plurality of routing nodes, each routing node being connected to selected ones of the other routing nodes and at least some of the routing nodes being connected to one of a plurality of packet sources or one of a plurality of packet destinations. Each routing node routes packets that are generated by the packet sources to respective ones of the packet destinations, each packet including a plurality of serially-transmitted cells. At least some of the routing nodes, in response to detection of a selected degree of congestion, enable an "early packet discard control arrangement," in which they discards cells which they receive which are related to packets for which they did not receive a cell prior to enabling the early packet discard control arrangement.

Abstract: In a pipeline data processor (11), an address pipeline (39, 41) id provided to hold the addresses of the instructions presently in the instruction pipeline (23, 25). The address pipeline facilitates tracing only executed instructions, and permits stopping the data processor during a branch delay slot without losing the branch information.

Abstract: The basic block division unit 2 divides the instruction sequence into basic blocks which are sequences with a continuous execution order. The control flow analysis unit 3 analyzes the control flow between basic blocks. The global equivalence relation analysis unit 4 traces the control flow between basic blocks and analyzes equivalence relations between resources, such as memory and registers, which cross over between basic blocks. The code is then optimized using these equivalence relations which cross over between basic blocks. In this way, the equivalence relations between resources in the program are analyzed globally and are used in the optimization of the code, so that a greatest possible reduction can be achieved in the code size and execution time of the program.

Abstract: An on-demand communication system provides a multimedia server connected to a plurality of clients via a network. A data stream can be transmitted in response to a transmission request of a title from a transmission device at the site of the client. The transmission device will transmit a set of reproduction information, including a plurality of titles and reproduction start times to the server along with the client identification. The server contemporarily would store, in a buffer, the reproduction information and the client identifier, read the reproduction information and the client identifier and then create a set of transmission information for each client request. A timer unit can activate a timer assigned to the client to measure time when the data stream transmission device is to start transmitting the data stream to the client.

Abstract: In a control system for controlling a very large number of remotely located input and output devices there is provided a novel control system having a single CPU coupled through a host interface module to a data and control transmission line. The host interface module on the transmission line receives information from and transmits information to a plurality of secondary interface modules having node addresses. The information being transmitted on the control and data transmission line is formatted to comprise one or two data bytes, an address and command byte, and an error checking byte to permit operation in a noisy electrical environment. Each said interface modules is further provided with high speed logic and an address counter for identifying node addresses and carrying out the commands and transmission of data without the requirement for software or firmware.

Abstract: An instruction sheet designer designs a handwriting sheet which allows execution of an arbitrary program by handwriting job instructions. The format of the handwriting sheet is stored as print data in a print data memory. If a job instruction is to be input, the handwriting sheet is printed on the basis of the print data stored in the print data memory or information based on the print data is displayed on the screen at a terminal. The job contents can be instructed in a look and feel manner in accordance with a sheet input, a key input, or a mouse input.

Abstract: A uniprocessing computer system is provided with an original CPU and an upgrade socket for receiving an additional processor that need not be of a single predetermined type. On system RESET, the original CPU determines if an upgrade processor is resident in the upgrade socket and, if so, what kind of upgrade processor is present. Each upgrade processor is equipped with a programmed data word for identifying the upgrade type and its features. The system includes a mechanism for communicating this upgrade information from the upgrade processor to the original CPU. The processors cooperatively configure the system properly according to the identity and features of the upgrade processor.