Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.

Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate, a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region, a metal gate disposed on and around the semiconductor channel region, and a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region.

Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.

Abstract: A method of forming a semiconductor device includes patterning a dielectric layer to form a groove and depositing a plurality of conductive layers over the dielectric layer and in the groove. The first conductive layer is a liner layer, the second conductive layer is a metal film, and the third conductive layer is a capping layer. The first conductive layer is treated with a hydrogen plasma treatment to remove impurities. The first conductive layer is also treated with a hydrogen soak treatment to remove microvoids. The third conductive layer is treated with an ammonia plasma treatment to remove impurities. The third conductive layer is also treated with a hydrogen plasma treatment to remove additional impurities. The third conductive layer is also treated with a hydrogen soak treatment to remove microvoids.

Abstract: A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.

Abstract: A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.

Abstract: A method of forming a film stack with reduced defects is provided and includes positioning a substrate on a substrate support within a processing chamber and sequentially depositing polysilicon layers and silicon oxide layers to produce the film stack on the substrate. The method also includes supplying a current of greater than 5 ampere (A) to a plasma profile modulator while generating a deposition plasma within the processing chamber, exposing the substrate to the deposition plasma while depositing the polysilicon layers and the silicon oxide layers, and maintaining the processing chamber at a pressure of greater than 2 Torr to about 100 Torr while depositing the polysilicon layers and the silicon oxide layers.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

Abstract: In a manufacturing method of a semiconductor device including a substrate having a front surface and a rear surface, and a film attached to the rear surface, the film is attached on the rear surface, a rear surface side groove is provided by half-cutting the substrate from the rear surface together with the film, a protective member is attached to the film after the rear surface side groove is provided, and a front surface side groove connected to the rear surface side groove is provided by dicing the substrate from the front surface after the protective member is attached.

Abstract: Systems, apparatus, and methods related to tamper-resistant integrated circuits are described. The tamper-resistant integrated circuits include tamper-resistant features including a tamper-resistant material formulated or configured to exhibit a change in at least one electrical property responsive to exposure to oxygen, electromagnetic radiation, or other environmental conditions. Data located within the integrated circuit may be erased, or at least a portion of the integrated circuit may be destroyed, responsive to a change in the at least one electrical property. In some examples, one or more electrical properties of a tamper-resistant feature may be measured. A change in an electrical property may be an indication that the associated integrated circuit has been tampered with.

Abstract: In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction.

Abstract: A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.

Abstract: A method for producing a sealed optical semiconductor device makes it possible to seal an optical semiconductor element using a sealing film. The method includes: placing a sealing film on an optical semiconductor element substrate on which an optical semiconductor element is placed within a pressure reduction chamber, and the pressure within the chamber is reduced; heating the film where at least the periphery of the film is thermally fused to the surface of the optical semiconductor element placement substrate; and a step in which the reduction of pressure within the chamber is released and the optical semiconductor element placement substrate is sealed by the film. The temperature T2 of the optical semiconductor element placement substrate when the reduction of pressure within the chamber is released is a temperature at which the film exhibits a tensile strength of 0.02-0.15 MPa and an elongation at break of 150-450%.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyly halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.

Abstract: A light-emitting device incorporates an electrode that includes conductive nanoparticles to increase emission performance. A light-emitting device includes a substrate; a first electrode disposed on the substrate between a viewing side of the light-emitting device and the substrate; a second electrode disposed between the first electrode and the viewing side of the light-emitting device, wherein the second electrode includes a layer of nanoparticles that are electrically conductive; and an emissive layer comprising quantum nanoparticles in electrical contact with the first electrode and the second electrode, wherein the first emissive layer includes a material that emits light when electrically excited. Multiple light-emitting devices may constitute sub-pixels that are combined into a pixel, such as for a display device, wherein each sub-pixel emits light of a different color.