Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: Thinning operating systems can include monitoring a number of functionalities of an operating system, the number of functionalities of the operating system being provided by a number of computing components loaded thereon. Thinning operating systems can include automatically identifying an undesired functionality of the number of functionalities during runtime and removing from the operating system at least one of the number of computing components providing the undesired functionality as a result of the automatic identification to thin the OS.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.

Abstract: Thinning operating systems can include monitoring a number of functionalities of an operating system, the number of functionalities of the operating system being provided by a number of computing components loaded thereon. Thinning operating systems can include automatically identifying an undesired functionality of the number of functionalities during runtime and removing from the operating system at least one of the number of computing components providing the undesired functionality as a result of the automatic identification to thin the OS.

Abstract: A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Abstract: A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

Abstract: A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address.

Abstract: A system comprises a plurality of cache agents, a computing entity coupled to the cache agents, and a programmable mask accessible to the computing entity. The programmable mask is indicative of, for at least one memory address, those cache agents that can receive a snoop request associated with a memory address. Based on the mask, the computing entity transmits snoop requests, associated with the memory address, to only those cache agents identified by the mask as cache agents that can receive a snoop request associated with the memory address.

Abstract: A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence oft he push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.

Abstract: A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled code having at least one thread, where each of the at least one thread includes a respective plurality of blocks and each respective block includes a respective pre-fetch component and a respective execute component. The method also includes performing a first pre-fetch component from a first block of a first thread of the at least one thread, performing a first additional component after the first pre-fetch component has been performed, and performing a first execute component from the first block of the first thread. The first execute component is performed after the first additional component has been performed, and the first additional component is from either a second thread or another block of the first thread that is not the first block.

Abstract: A system comprising a first subsystem adapted to provide a service by executing a first code stored on the first subsystem. The system further comprises a second subsystem, communicably coupled to the first subsystem, on which a second code associated with the first code is stored. The second subsystem produces modified code by applying status files associated with the first code to the second code. The second subsystem provides the service in lieu of the first subsystem by executing the modified code.

Abstract: Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.

Abstract: A cache memory system can determine that an entry is stale if the entry has not been accessed or modified for a predetermined time. If an entry is stale, the entry may be preemptively evicted. The predetermined time is made dynamically variable. A computer system can adjust the time to optimize a measure of performance. In a specific example, evicted lines are temporarily stored in an eviction queue. The time is adjusted to be as short as possible without substantially increasing the number of lines that must be recalled from the eviction queue.

Abstract: A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may be further improve performance by limiting the number of dirty entries in a cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-cache transfer when the number exceeds a predetermined threshold. For either system, the predetermined threshold may be dynamically varied to determine a value that optimizes performance.

Abstract: A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may further improve performance by limiting the number of dirty entries in the cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-ache transfer when the number exceeds a predetermined threshold.

Abstract: A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system processes are moved from the affected CPU coupled to the failing cooling device to one or more other CPUs. The system state is then altered so that interrupts are no longer received and processed by the affected CPU, and all memory caches associated with the affected CPU are flushed back to main memory to ensure cache coherency. At this point, the CPU is either powered-down, or placed in a low-power mode that allows the CPU to operate without the cooling device, while the processes that were removed from the suspended CPU continue executing on other CPUs.

Abstract: In a method of managing memory, a plurality of check values are generated from contents of memory. Each check value is associated with a respective page in a memory system in a data structure. The data structure is searched for a candidate page having identical content to a requesting page in the memory system by utilizing a check value of the requested page in the search.

Abstract: A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may be further improve performance by limiting the number of dirty entries in a cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-cache transfer when the number exceeds a predetermined threshold. For either system, the predetermined threshold may be dynamically varied to determine a value that optimizes performance.