Patents by Inventor A Leam Choi

A Leam Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8970044
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 3, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: A Leam Choi, DongSam Park, YongDuk Lee
  • Patent number: 8699232
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, DeokKyung Yang, JoHyun Bae
  • Patent number: 8569869
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having an elevated portion and a hole adjacent to the elevated portion with the elevated portion over the integrated circuit and the rounded interconnect exposed from the hole; and forming an encapsulation between the conductive shield and the package carrier with the rounded interconnect exposed.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: October 29, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: HyungSang Park, A Leam Choi, JoHyun Bae
  • Patent number: 8558366
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Kenny Lee, In Sang Yoon, HanGil Shin
  • Publication number: 20130070438
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Inventors: A Leam Choi, DeokKyung Yang, JoHyun Bae
  • Publication number: 20120326325
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Inventors: A Leam Choi, DongSam Park, YongDuk Lee
  • Publication number: 20120223435
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base integrated circuit over a base substrate; stacking a mountable device over the base package with a flow channel between the mountable device and the base package; and forming an external lead having a lead platform and a lead leg, the lead platform extending from the mountable device and the lead leg parallel to the base package.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang
  • Patent number: 8183089
    Abstract: A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 22, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Young Jin Woo, Junwoo Myung
  • Publication number: 20120086115
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 12, 2012
    Inventors: A Leam Choi, Kenny Lee, In Sang Yoon, HanGil Shin
  • Patent number: 8106498
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 31, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: HanGil Shin, HeeJo Chi, A Leam Choi
  • Patent number: 8093100
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Patent number: 8080446
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; and forming an encapsulation that encapsulates the integrated circuit, the routing structure.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: December 20, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: A Leam Choi, Kenny Lee, In Sang Yoon, HanGil Shin
  • Publication number: 20110233736
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having an elevated portion and a hole adjacent to the elevated portion with the elevated portion over the integrated circuit and the rounded interconnect exposed from the hole; and forming an encapsulation between the conductive shield and the package carrier with the rounded interconnect exposed.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Inventors: HyungSang Park, A Leam Choi, JoHyun Bae
  • Patent number: 8008787
    Abstract: An integrated circuit package system includes: mounting an integrated circuit die over a carrier; attaching a delamination prevention structure over the integrated circuit die; and encapsulating the delamination prevention structure and the integrated circuit die.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: August 30, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DongSam Park, A Leam Choi, Keon Teak Kang
  • Publication number: 20110092021
    Abstract: A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Inventors: A Leam Choi, Young Jin Woo, Junwoo Myung
  • Publication number: 20110062591
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Application
    Filed: November 19, 2010
    Publication date: March 17, 2011
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Patent number: 7859099
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Patent number: 7859120
    Abstract: A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Young Jin Woo, Junwoo Myung
  • Publication number: 20100301469
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; and forming an encapsulation that encapsulates the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 2, 2010
    Inventors: A Leam Choi, Kenny Lee, In Sang Yoon, HanGil Shin
  • Publication number: 20100224975
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.
    Type: Application
    Filed: March 5, 2009
    Publication date: September 9, 2010
    Inventors: HanGil Shin, HeeJo Chi, A Leam Choi