Patents by Inventor Aaron K. Olbrich

Aaron K. Olbrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8533384
    Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 10, 2013
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Patent number: 8484533
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: July 9, 2013
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Aaron K. Olbrich, Doug Prins
  • Patent number: 8484534
    Abstract: In a multiple level cell flash memory data storage device, a flash memory array has a plurality of blocks, where each block is an erase unit and has a plurality of pages, and a respective block includes a plurality of groups of pages. Each group of pages in the respective block includes an assigned parity page, and each page of the respective block has a plurality of sectors, including an assigned parity sector. The storage device is operable to program and erase data on a page at a predetermined speed, and detect an error rate for each page of a block and identify a group of high error pages based on the error rates. Further, the storage device is configured to apply a speed slower than the predetermined speed in programming and erasing data on the identified high error pages.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: July 9, 2013
    Assignee: Sandisk Enterprise IP LLC.
    Inventors: Aaron K. Olbrich, Doug Prins
  • Patent number: 8473814
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 25, 2013
    Assignee: SanDisk Enterprise IP LLC
    Inventors: Aaron K. Olbrich, Doug Prins
  • Publication number: 20130145229
    Abstract: An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments.
    Type: Application
    Filed: November 16, 2012
    Publication date: June 6, 2013
    Inventors: Jack Edward Frayer, Aaron K. Olbrich
  • Publication number: 20130145231
    Abstract: An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.
    Type: Application
    Filed: November 16, 2012
    Publication date: June 6, 2013
    Inventors: Jack Edward Frayer, Aaron K. Olbrich
  • Publication number: 20130132804
    Abstract: An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 23, 2013
    Inventors: Jack Edward Frayer, Aaron K. Olbrich
  • Patent number: 8386700
    Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: February 26, 2013
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Patent number: 8365041
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: January 29, 2013
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Aaron K. Olbrich, Doug Prins
  • Publication number: 20120272106
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 25, 2012
    Inventors: Aaron K. Olbrich, Doug Prins
  • Publication number: 20120266032
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Inventors: Aaron K. Olbrich, Doug Prins
  • Publication number: 20120266052
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Application
    Filed: June 27, 2012
    Publication date: October 18, 2012
    Inventors: Aaron K. Olbrich, Doug Prins
  • Patent number: 8245101
    Abstract: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: August 14, 2012
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Publication number: 20120072654
    Abstract: A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Publication number: 20110228601
    Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 22, 2011
    Inventors: Aaron K. Olbrich, Doug Prins
  • Patent number: 7978516
    Abstract: Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 12, 2011
    Assignee: Pliant Technology, Inc.
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Patent number: 7934052
    Abstract: Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: April 26, 2011
    Assignee: Pliant Technology, Inc.
    Inventors: Douglas A. Prins, Aaron K. Olbrich
  • Publication number: 20090172259
    Abstract: A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.
    Type: Application
    Filed: April 8, 2008
    Publication date: July 2, 2009
    Inventors: Douglas A. Prins, Aaron K. Olbrich
  • Publication number: 20090172308
    Abstract: A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.
    Type: Application
    Filed: April 8, 2008
    Publication date: July 2, 2009
    Inventors: Douglas A. Prins, Aaron K. Olbrich
  • Publication number: 20090168525
    Abstract: Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.
    Type: Application
    Filed: April 8, 2008
    Publication date: July 2, 2009
    Inventors: Aaron K. Olbrich, Douglas A. Prins