Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: An electronic device may include a display and an optical sensor formed underneath the display. A pixel removal region on the display may at least partially overlap with the sensor. The pixel removal region may include a plurality of non-pixel regions each of which is devoid of thin-film transistors. The plurality of non-pixel regions is configured to increase the transmittance of light through the display to the sensor. In addition to removing thin-film transistors in the pixel removal region, additional layers in the display stack-up may be removed. In particular, a cathode layer, polyimide layer, and/or substrate in the display stack-up may be patterned to have an opening in the pixel removal region. A polarizer may be bleached in the pixel removal region for additional transmittance gains. The cathode layer may be removed using laser ablation with a spot laser or blanket illumination.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: An electronic device may include a display and a sensor under the display. The display may include pixels having emission transistors that are controlled by emission signals. The emission signals are controlled using a pulse width modulation (PWM) scheme to control the brightness of the display. The emission signals may further include a localized sensor blackout pulse configured to generate a localized sensor blackout region that overlaps with the sensor to reduce any undesired back emission of light emitted from the display. The sensor blackout pulse may be automatically generated periodically or generated in an on-demand basis once per frame, multiple times per frame time, or once every multiple frames. Any luminance degradation caused by the sensor blackout pulse may be compensated by boosting the luminance and/or by extending the duration of each emission on pulse.

Abstract: Visibility of the metal mesh touch electrodes can be mitigated using one or more mitigation techniques. In some examples, the boundary between touch electrodes and/or the boundary between a touch electrode and a routing trace of another touch electrode and/or the boundary between two routing traces can be non-linear. In some examples, dummy cuts can be made within an area of a touch electrode region (e.g., while maintaining the same electrical potential for the touch electrode region). In some examples, notches can be made in the metal mesh. In some examples, the location of cuts and/or notches can be optimized to mitigate visibility of the metal mesh. In some examples, some or all of the visibility mitigations may be used in combination in a touch screen.

Abstract: Visibility of the metal mesh touch electrodes can be mitigated using one or more mitigation techniques. In some examples, the boundary between touch electrodes and/or the boundary between a touch electrode and a routing trace of another touch electrode and/or the boundary between two routing traces can be non-linear. In some examples, dummy cuts can be made within an area of a touch electrode region (e.g., while maintaining the same electrical potential for the touch electrode region). In some examples, notches can be made in the metal mesh. In some examples, the location of cuts and/or notches can be optimized to mitigate visibility of the metal mesh. In some examples, some or all of the visibility mitigations may be used in combination in a touch screen.

Abstract: An electronic device may include a display and a sensor under the display. The display may include an array of subpixels for displaying an image to a user of the electronic device. At least a portion of the array of subpixels may be selectively removed in a pixel removal region to improve optical transmittance to the sensor through the display. The pixel removal region may include a plurality of pixel free regions that are devoid of thin-film transistor structures, that are devoid of power supply lines, that have continuous open areas due to rerouted row/column lines, that are partially devoid of touch circuitry, that optionally include dummy contacts, and/or have selectively patterned display layers.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: An electronic device display may have pixels formed from crystalline semiconductor light-emitting diode dies, organic light-emitting diodes, or other pixel structures. The pixels may be formed on a display panel substrate. A display panel may extend continuously across the display or multiple display panels may be tiled in two dimensions to cover a larger display area. Interconnect substrates may have outwardly facing contacts that are electrically shorted to corresponding inwardly facing contacts such as inwardly facing metal pillars associated with the display panels. The interconnect substrates may be supported by glass layers. Integrated circuits may be embedded in the display panels and/or in the interconnect substrates. A display may have an active area with pixels that includes non-spline pixels in a non-spline display portion located above a straight edge of the display and spline pixel in a spline display portion located above a curved edge of the display.

Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

Abstract: An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.

Abstract: An organic light-emitting diode display may have thin-film transistor circuitry formed on a substrate. The display and substrate may have rounded corners. A pixel definition layer may be formed on the thin-film transistor circuitry. Openings in the pixel definition layer may be provided with emissive material overlapping respective anodes for organic light-emitting diodes. A cathode layer may cover the array of pixels. A ground power supply path may be used to distribute a ground voltage to the cathode layer. The ground power supply path may be formed from a metal layer that is shorted to the cathode layer using portions of a metal layer that forms anodes, may be formed from a mesh shaped metal pattern, may have L-shaped path segments, and may include laser-deposited metal on the cathode layer. Data lines may be formed from metal layers in the active area to accommodate the rounded corners of the display.

Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

Abstract: A self-capacitive touch sensor panel configured to have a portion of both the touch and display functionality integrated into a common layer is provided. The touch sensor panel includes a layer with circuit elements that can switchably operate as both touch circuitry and display circuitry such that during a touch mode of the device the circuit elements operate as touch circuitry and during a display mode of the device the circuit elements operate as display circuitry. The touch mode and display mode can be time multiplexed. By integrating the touch hardware and display hardware into common layers, savings in power, weight and thickness of the device can be realized.

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.