Abstract: Various embodiments disclosed relate to a semiconductor assembly having a ceramic or glass interposer for connecting dies within a semiconductor package. The present disclosure includes a ceramic or glass interposer having a carrier layer of substantially glass or ceramic material and a connecting layer having at least one dielectric layer and electrical routing therein.

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

Abstract: An electronic device comprises a substrate including an organic material; a glass bridge die included in the substrate, the glass bridge die including electrically conductive interconnect; and a first integrated circuit (IC) die and at least a second IC die arranged on a surface of the substrate and including bonding pads connected to the interconnect of the glass bridge die.

Abstract: An electronic device comprises a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material; a stiffening layer including one of a ceramic or glass, the stiffening layer including a first surface contacting a first surface of the first RDL and including a through layer via (TLV); and multiple integrated circuit (ICs) arranged on a second surface of the first RDL and including bonding pads, wherein the conductive traces of the first RDL provide electrical continuity between at least one bonding pad of the ICs and at least one TLV of the stiffening layer.

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface; a die electrically coupled to the second surface of the substrate; and a stiffener attached to the first surface of the substrate configured to mitigate warpage of the die.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate, including a core and a stiffener in the core, wherein the stiffener is along a perimeter of the core; and a die electrically coupled to the substrate.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; and a microelectronic subassembly electrically coupled to the substrate by interconnects, the microelectronic subassembly including an interposer having a surface; a first die electrically coupled to the surface of the interposer; a second die electrically coupled to the surface of the interposer; and a stiffener ring coupled to the surface of the interposer along the perimeter of the interposer.

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

Abstract: A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.

Abstract: A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices.

Abstract: A memory module with a module board is disclosed, on the front side of which a plurality of first memory devices are arranged in rows. A plurality of second memory devices are arranged in rows on the back side. The first and second memory devices have a single chip each. Further, a first register device for providing first control signals to first rows of first memory devices and to first rows of second memory devices is provided. A second register device serves to provide first control signals to second rows of first memory devices and to second rows of second memory devices.

Abstract: A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units.

Abstract: An electronic system with integrated circuit device and passive component is disclosed. One embodiment provides a printed circuit board, a method for fabricating an electronic system, and an electronic system, including at least one integrated circuit device and at least one passive component, wherein the passive component is arranged at least partially underneath the integrated circuit device.

Abstract: In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a connector strip, which runs at a first edge of the at least one outer face in a first direction and has a multiplicity of electrical contacts that are lined up in the first direction. The printed circuit board extends in the first direction between two opposite second edges. At least nine of the semiconductor chips of the same type are respectively mounted next to one another on the outer face of the printed circuit board between the center of the printed circuit board and the respective second edge of the printed circuit board. The semiconductor chips of the same type respectively have a smaller dimension and, in the direction perpendicular to the smaller dimension, a larger dimension that is larger than the smaller dimension.

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

Abstract: A memory module includes a first printed circuit board, wherein some of the memory chips in each of first and second ranks of memory chips are assembled on one side of the printed circuit board and others of the first and second ranks are assembled on the other side of the printed circuit board. First and second registers are respectively connected to the first and second address buses for respectively addressing the first and second ranks of memory chips. Since the addresses buses are separate for the two ranks, it is possible to activate only the address bus associated with the particular rank being addressed. In this manner, address activation power is saved by not activating the address bus of the other rank which is not addressed. Due to less power dissipation, it is possible to operate the memory module without a full DIMM heat spreader.

Abstract: A memory module includes a first pc-board with a plurality of memory chips assembled thereon and with a second pc-board with a second plurality of memory chips assembled thereon. The first pc-board and the second pc-board are connected via first and second connectors placed on the surfaces of the first and second pc-boards.

Abstract: In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a connector strip, which runs at a first edge of the at least one outer face in a first direction and has a multiplicity of electrical contacts that are lined up in the first direction. The printed circuit board extends in the first direction between two opposite second edges. At least nine of the semiconductor chips of the same type are respectively mounted next to one another on the outer face of the printed circuit board between the center of the printed circuit board and the respective second edge of the printed circuit board. The semiconductor chips of the same type respectively have a smaller dimension and, in the direction perpendicular to the smaller dimension, a larger dimension that is larger than the smaller dimension.