Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

Abstract: In an aspect, a semiconductor includes a substrate. The substrate includes a column comprising a conductive paste that passes through a plurality of metal layers, a resin sheath surrounding the column, a ground shield surrounding the resin sheath, and a plurality of sense lines. The plurality of sense lines include a first sense line that is connected to the column comprising the conductive paste and a second sense line that is connected to the ground shield. The resin comprises a dielectric material.

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

Abstract: A device that includes an integrated device, a plurality of solder interconnects, and an integrated passive device (IPD). The integrated device includes a die having a front side and back side, and a metallization portion coupled to the front side of the die. The metallization portion includes at least one metallization layer and a plurality of under bump metallization (UBM) interconnects. The plurality of solder interconnects is coupled to the metallization portion. The integrated passive device (IPD) is coupled to the metallization portion of the integrated device such that the IPD is located between at least two solder interconnects from the plurality of solder interconnects.

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

Abstract: The invention discloses an apparatus for reducing peak temperatures and thermal excursions, of semiconductor devices, particularly in pulsed power applications. The apparatus comprises thermally coupling Phase Change Material (PCM) to the dissipating semiconductor device. PCM absorbs heat and stays at a constant temperature during its phase change from solid to liquid. The PCM melting point is chosen so that it is just below the temperature the device would otherwise achieve. When the device approaches the maximum temperature, the PCM melts, drawing heat from the device and lowering the device's peak temperature. As the device stops dissipating, after its pulse period, the PCM material solidifies releasing the heat it absorbed. The apparatus lowers the peak temperature by absorbing heat when the device is dissipating.

Abstract: Method and structure for temperature stabilization in semiconductor devices are disclosed. In one embodiment, a carbon-based polymer is deposited on top of an interconnect metal line in the semiconductor die where relatively large power dissipation is known to occur. Reduction of the range of temperature excursions in the semiconductor die is achieved since the polymer acts as a cushion to dampen the range of temperature excursions of the semiconductor die. During occurrence of power pulses in the semiconductor die, the polymer absorbs energy from the interconnect metal, and thus from the semiconductor devices that are connected to the interconnect metal, by expanding without a rise in the temperature of the polymer. The energy generated when power pulses are being dissipated in the semiconductor die does not result in a substantial rise in the temperature of the polymer.

Abstract: Phase Change Material (“PCM”) are used to reduce the range of temperature excursions in a semiconductor die attached to an interconnect substrate in the flip chip technology. In one embodiment a PCM underfill, which comprises PCM microspheres interspersed within a polymer, is dispensed in the interface area between the semiconductor die and the interconnect substrate. Reduction of the range of temperature excursions in the semiconductor die is achieved since the PCM underfill acts as a cushion to dampen the range of temperature excursions of the semiconductor die. During dissipation of power pulses in the semiconductor die, the PCM underfill absorbs energy from the semiconductor die by changing phase from solid to liquid without a concomitant rise in the temperature of the PCM underfill. Thus, the energy released when power pulses are being dissipated in the semiconductor die does not result in a rise in the temperature of the PCM underfill.

Abstract: Phase Change Material (“PCM”) are used to reduce the range of temperature excursions in a semiconductor die attached to an interconnect substrate in the flip chip technology. In one embodiment a PCM underfill, which comprises PCM microspheres interspersed within a polymer, is dispensed in the interface area between the semiconductor die and the interconnect substrate. Reduction of the range of temperature excursions in the semiconductor die is achieved since the PCM underfill acts as a cushion to dampen the range of temperature excursions of the semiconductor die. During dissipation of power pulses in the semiconductor die, the PCM underfill absorbs energy from the semiconductor die by changing phase from solid to liquid without a concomitant rise in the temperature of the PCM underfill. Thus, the energy released when power pulses are being dissipated in the semiconductor die does not result in a rise in the temperature of the PCM underfill.

Abstract: The invention discloses an apparatus for cooling semiconductors which are mounted on substrates for the purpose of packaging. In some electronic packaging methods semiconductor dies are mounted on substrates instead of being encapsulated and mounted individually on circuit boards. This method can be beneficial from both cost and manufacturing standpoints but can lead to problems when semiconductor power chips on the substrate generate enough heat to cause excess heating of themselves and adjacent chips on the substrate. The invention discloses several methods of removing heat from the power chips in order to minimize the temperature within the semiconductor die and to minimize the conduction of heat to other devises mounted on the substrate. The invention involves using thermal vias (thermally conducting pathways) embedded in the substrate and circuit board on which the substrate sits to conduct heat from the semiconductor and away from the substrate.