Patents by Inventor Abdulrahman Mahmoud

Abdulrahman Mahmoud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817289
    Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 27, 2020
    Assignee: NVIDIA Corp.
    Inventors: Siva Hari, Michael Sullivan, Timothy Tsai, Stephen W. Keckler, Abdulrahman Mahmoud
  • Publication number: 20190262165
    Abstract: The self-adjusting tool (10) for correcting ingrown toenail uses self-adjusting elastic tension to lift the ingrown ends (N1, N2) of an ingrown toenail (N). In a first embodiment, the self-adjusting tool (10) includes two identical leaf springs (12a, 12b), each having a flat end (16a, 16b) and a band (14a, 14b) forming a flat loop at the opposite end. The two springs (12a, 12b) are interlocked by sliding the flat end (16a, 16b) of one spring through the band (14a, 14b) of the other, and the free ends (16a, 16b) are glued to lateral edges of the ingrown toenail (N) to flatten the toenail (N) by self-adjusting elastic tension. Other embodiments show at least one resilient member flexed across the ingrown toenail and anchored at opposite lateral edges on the ingrown toenail to pull the ingrown edges of the toenail away from engagement with the toe.
    Type: Application
    Filed: January 23, 2018
    Publication date: August 29, 2019
    Inventor: ABDULRAHMAN MAHMOUD ABDULLAH AL SUWAIDI
  • Publication number: 20190102180
    Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra -thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 4, 2019
    Inventors: Siva Hari, Michael Sullivan, Timothy Tsai, Stephen W. Keckler, Abdulrahman Mahmoud