Abstract: A system for pre-boot authentication of a virtual appliance includes one or more subsystems to receive a command to power-on an information handling system (IHS). After receiving the command to power-on the IHS, the system initializes a power-on self test (POST), passes control of the IHS to a hypervisor, loads a concurrent service environment (CSE), requests user credentials, receives user credentials, authenticates user credentials using the CSE and authorizes a specific operating system image from a plurality of images to run on the IHS via the virtual appliance after the user credentials are authenticated.

Abstract: Systems and methods for executing tasks on a managed node remotely coupled to a management node are provided. A management controller of the management node may be configured to determine at least one execution policy for a task, schedule the task for execution, receive system information data from the managed node, based at least on the received system information, determine if the received system information complies with the at least one execution policy, and if the received information complies with the at least one execution policy, forward the task from the management controller to the managed node for execution.

Abstract: A system for pre-boot authentication of a virtual appliance includes one or more subsystems to receive a command to power-on an information handling system (IHS). After receiving the command to power-on the IHS, the system initializes a power-on self test (POST), passes control of the IHS to a hypervisor, loads a concurrent service environment (CSE), requests user credentials, receives user credentials, authenticates user credentials using the CSE and authorizes a specific operating system image from a plurality of images to run on the IHS via the virtual appliance after the user credentials are authenticated.

Abstract: Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

Abstract: A system and method is disclosed for a distributed out-of-band (OOB) management controller system enabling efficient usage of power while providing multiple methods and levels of communication between intelligent devices. Two or more management controllers collaboratively operate in a predetermined manner including, but not limited to, peer-to-peer, master/slave, or independently. Management information consistency is maintained across a system's power states by implementing distributed intelligent devices that directly interact as communication devices to local or remote management consoles. A management protocol is implemented such that management information is communicated between managed elements and management controllers over physical interfaces or via a network connection.

Abstract: Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

Abstract: A methodology may be used that takes into account the inductive coupling of current transients on the power rails of a printed circuit board (PCB) that may be coupled to the barrel of a via. By taking into account the coupling of the current transients on the power rails of the PCB, more accurate and realistic modeling results may be obtained. Inductive coupling of the current transients from the power rails may be more pronounced at higher frequencies and may be additive for more layer transitions (e.g., more via transitions) of the PCB.

Abstract: Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

Abstract: An information handling system that includes a circuit board for mounting and coupling components of the information handling system. The circuit board includes a trace, a via coupled to the trace, and a cutout region surrounding the via and having a first diameter selected to minimize a loading effect of a via on a signal conveyed on the trace.

Abstract: A method and system for reporting detected errors in a computer system. The computer system includes a processor, communication device, and subsystems. The communication device preferably includes a preprogrammed reporting address associated with a technical support center. When an error is detected within the system, an error specific message is generated. The communication device then sends the error message to the preprogrammed address. The technical support center, resident at the preprogrammed address receives the error message and is able to more effectively respond to the detected error message.

Abstract: An information handling system that includes a circuit board for mounting and coupling components of the information handling system. The circuit board includes a trace, a via coupled to the trace, and a cutout region surrounding the via and having a first diameter selected to minimize a loading effect of a via on a signal conveyed on the trace.

Abstract: A multi-layer circuit substrate having an integral bus portion includes a dielectric substrate having a first device signal layer formed on a first side thereof and a second device signal layer formed on a second side thereof. The first and second device signal layers are each patterned to include at least one bus reference plane. A device reference plane layer is disposed between the first and second device signal layers in the dielectric substrate. The device reference plane layer is patterned to include a plurality of guard bands and a bus signal trace between at least two of the guard bands.

Abstract: A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer.

Abstract: In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses from the peripheral device is disclosed. The buffer is included in a bridge device for interfacing the two computer buses and controlling when the peripheral device may access the main memory. When the peripheral device attempts to read data from the main memory that is duplicated in the cache and that has become stale, the bridge device initiates a write back operation to update specific data portions of the main memory corresponding to the read request. The bridge device uses look-ahead techniques such as bursting or pipelining to streamline the data coming from the cache to the main memory and to the peripheral device.