Abstract: Approaches for preserving customizations made to a data management system. Metadata that identifies a mapping between data fields of one or more data source schemas to columns of one or more data tier schemas is maintained. Each of the one or more data tier schemas stores data retrieved from the one or more data source schemas. Values from the metadata are read to dynamically generate software processes. The software processes may update one or more existing ETL processes to reflect an updated state of the one or more data tier schemas and may generate any new ETL processes required to retrieve data stored in the one or more data source schemas and load the retrieved data into the one or more data tier schemas. Customizations made to portions the data management system are preserved in an automated fashion when new versions of system components are deployed.

Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the selected at least one design variable and in response to the simulation, automatically displaying an updated value at the graphical user interface.

Abstract: Exemplary methods, apparatuses, and systems receive a first input/output (I/O) trace from a first workload and run the first I/O trace through a cache simulation to determine a first miss ratio curve (MRC) for the first workload. A second I/O trace from the first workload is received and run through the cache simulation to determine a second MRC for the first workload. First and second cache sizes corresponding to a target miss rate for the first workload are determined using the first and second MRCs. A fingerprint of each of the first and I/O traces is generated. The first cache size, the second cache size, or a combination of the first and second cache sizes is selected as a cache size for the first workload based upon a comparison of the first and second fingerprints. A recommended cache size is generated based upon the selected cache size.

Abstract: Exemplary methods, apparatuses, and systems receive a first input/output (I/O) trace from a first workload and run the first I/O trace through a cache simulation to determine a first miss ratio curve (MRC) for the first workload. A second I/O trace from the first workload is received and run through the cache simulation to determine a second MRC for the first workload. First and second cache sizes corresponding to a target miss rate for the first workload are determined using the first and second MRCs. A fingerprint of each of the first and I/O traces is generated. The first cache size, the second cache size, or a combination of the first and second cache sizes is selected as a cache size for the first workload based upon a comparison of the first and second fingerprints. A recommended cache size is generated based upon the selected cache size.

Abstract: The rate at which packets are provided to a cryptographic engine of a cryptographic system is adjusted using a feedback mechanism to increase the output of the cryptographic system. Data is classified and queued on a per class/flow basis and stored in input queues prior to being processed. A class based queue scheduler is implemented to select data from the input queues to be transmitted to the cryptographic engine. The cryptographic engine operates in processing cycles. At each cycle, an amount of data is transferred from the input queues to a cryptographic engine input queue. A cryptographic accelerator in the cryptographic engine processes the data on the cryptographic engine input queue during the cycle. The output rate of the cryptographic accelerator is measured during the cycle and this value is used as feedback to determine how much data should be passed to the cryptographic engine for a subsequent cycle.

Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

Abstract: A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and any space in the bounded region of the display needed to display such information is acquired by a decrease in the amount of information provided by the data items outside the context.

Abstract: The rate at which packets are provided to a cryptographic engine of a cryptographic system may be adjusted using a feedback mechanism to increase the output of the cryptographic system. Data is classified and queued on a per class/flow basis and stored in input queues prior to being processed by the cryptographic engine. A class based queue scheduler is implemented to select data from the input queues to be transmitted to the cryptographic engine. The cryptographic engine operates in processing cycles. At each cycle, an amount of data is transferred from the input queues to a cryptographic engine input queue. A cryptographic accelerator in the cryptographic engine processes the data on the cryptographic engine input queue during the cycle. The output rate of the cryptographic accelerator is measured during the cycle and this value is used as feedback to determine how much data should be passed to the cryptographic engine for a subsequent cycle.

Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

Abstract: A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and any space in the bounded region of the display needed to display such information is acquired by a decrease in the amount of information provided by the data items outside the context.