Patents by Inventor Abha Singh
Abha Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240163375Abstract: Methods, systems, apparatuses, and computer-readable storage mediums described herein are configured to transfer call context between different call center systems. For example, a first call center system that establishes a communication session between a user and an agent of the first system provides context determined during the session to a call context service. The service stores the context and provides it to other requesting call center systems. For instance, during a call transfer to an agent of a second system, the first system requests the service to provide a transfer number of the second system to which the user is to be transferred. The service determines the transfer number and provides it to the first system. The first system performs the call transfer using the number. After the transfer is complete, the second system provides a request for the context, and the service provides the context to the second system.Type: ApplicationFiled: June 19, 2023Publication date: May 16, 2024Inventors: Shiva AGARWAL, Alexander Adam FENNELL, Anabela da Silva Carvalho HELISZKOWSKI, Hayley Kara HOWELL, Peter Burr NILSSON, Puneet Singh SOHI, Daniel Blaine THORINGTON, Stephanie Ann ENGLISH, Sathak Abdul Hameed SATHAKATHULLA, Abhas BRAHMA
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Patent number: 9978712Abstract: A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P1), a second input pin (P2), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.Type: GrantFiled: May 25, 2016Date of Patent: May 22, 2018Assignee: Texas Instruments IncorporatedInventors: Danyang Zhu, Zhuang Ma, Xinyu Yin, Michael Dean Shilhanek, Steven Bolen, Albert Eardley, Abha Singh Kasper
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Publication number: 20170194285Abstract: A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P1), a second input pin (P2), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.Type: ApplicationFiled: May 25, 2016Publication date: July 6, 2017Inventors: DANYANG ZHU, ZHUANG MA, XINYU YIN, MICHAEL DEAN SHILHANEK, STEVEN BOLEN, ALBERT EARDLEY, ABHA SINGH KASPER
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Publication number: 20160245861Abstract: Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.Type: ApplicationFiled: March 2, 2016Publication date: August 25, 2016Inventors: Stanton Petree Ashburn, Daniel L. Corum, JR., Abha Singh Kasper, Harold C. Waite, Eric D. Rullan, Donald L. Plumton, Douglas A. Prinslow
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Patent number: 9378848Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.Type: GrantFiled: June 7, 2012Date of Patent: June 28, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Stanton Petree Ashburn, Daniel L. Corum, Abha Singh Kasper, Harold C. Waite, Eric D. Rullan, Donald L. Plumton, Douglas A. Prinslow
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Patent number: 9305664Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.Type: GrantFiled: March 26, 2014Date of Patent: April 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Beena Pious, Stanton Petree Ashburn, Abha Singh Kasper
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Publication number: 20150279487Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Applicant: Texas Instruments IncorporatedInventors: Beena Pious, Stanton Petree Ashburn, Abha Singh Kasper
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Publication number: 20130329508Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.Type: ApplicationFiled: June 7, 2012Publication date: December 12, 2013Applicant: Texas Instruments IncorporatedInventors: Stanton Petree Ashburn, Daniel L. Corum, Abha Singh Kasper, Harold C. Waite, Eric D. Rullan, Donald L. Plumton, Douglas A. Prinslow
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Patent number: 6687973Abstract: A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).Type: GrantFiled: November 30, 2001Date of Patent: February 10, 2004Assignee: Texas Instruments IncorporatedInventors: Melissa M. Hewson, Ricky A. Jackson, Abha Singh, Toan Tran, Howard L. Tigelaar
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Publication number: 20020062549Abstract: A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).Type: ApplicationFiled: November 30, 2001Publication date: May 30, 2002Inventors: Melissa M. Hewson, Ricky A. Jackson, Abha Singh, Toan Tran, Howard L. Tigelaar