Abstract: A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P1), a second input pin (P2), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.

Abstract: A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P1), a second input pin (P2), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.

Abstract: Devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment includes a die which has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have intentionally induced defects that form a predetermined fault pattern.

Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.

Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.

Abstract: Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.