Abstract: Embodiments of a memory device are disclosed that may allow for detecting the opportunity for energy savings and implementing the energy savings for each access to the memory device. The memory device may include a plurality of columns, an address comparator, and a timing and control circuit. Each of the plurality of columns may include a plurality of data storage cells coupled to a common data line, and a pre-charge circuit that may be configured to charge the common data line to a pre-determined voltage. The address comparator may be configured to compare an address value to a previous address value, and generate an output dependent upon the comparison. The timing and control circuit may then selectively disable pre-charge circuits in the plurality of columns dependent upon the generated output of the address comparator.

Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

Abstract: Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.

Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

Abstract: Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.

Abstract: A dynamic, content addressable memory (CAM) cell includes a match line, a write line, a first pair of complementary bit lines for read and search operations, and a second pair of complementary bit lines for write operations; a first storage transistor connected between one of the first pair of complementary bit lines and the match line; a second storage transistor connected between the other of the first pair of complementary bit lines and the match line; a first write transistor connected between a gate of the first storage transistor and one of the second pair of complementary bit lines; and a second write transistor connected between a gate of the second storage transistor and the other of the second pair of complementary bit lines, with both the first and second write transistors having a gate connected to the write line.

Abstract: A method of testing critical paths in integrated circuits begins by simulating at least one operation of an integrated circuit chip design to produce chip timing data. Next, critical paths of the integrated circuit chip design are identified based on the chip timing data. The method applies functional test signals to simulations of the critical paths and monitors the number of times each of the functional test signals propagate from the beginning to the end of each of the critical paths. This allows the method to identify stress producing test signals as those that propagate along the critical paths more than other test signals. These stress producing test signals are applied to integrated circuit chip hardware manufactured according to the integrated circuit chip design to stress test the hardware.