Abstract: One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias.

Abstract: One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias.