Patents by Inventor Abhijit Pethe

Abhijit Pethe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170062522
    Abstract: Provided are selector elements having snapback characteristics and non-volatile memory cells comprising such selector elements. To achieve its snapback characteristic, a selector element may include a dielectric layer comprising an alloy of two or more materials. In the same or other embodiments, the selector element may include a doped electrode, such carbon electrodes doped with silicon, germanium, and/or selenium. Concentrations of different materials forming an alloy may vary throughout the thickness of the dielectric layer. For example, the concentration of the first one alloy material may be higher in the center of the dielectric layer than near the interfaces of the dielectric layer with the electrodes. Some examples of this alloy material include germanium, indium, and aluminum. Examples of other materials in the same alloy include silicon, gallium, arsenic, and antimony. In some embodiments, the alloy is formed by three or more elements, such as indium gallium arsenic.
    Type: Application
    Filed: August 12, 2016
    Publication date: March 2, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Salil Mujumdar, Abhijit Pethe, Ashish Bodke, Kevin Kashefi
  • Publication number: 20160181380
    Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Amol Joshi, Sean Barstow, Paul Besser, Ashish Bodke, Guillaume Bouche, Nobumichi Fuchigami, Zhendong Hong, Shaoming Koh, Albert Sanghyup Lee, Salil Mujumdar, Abhijit Pethe, Mark Victor Raymond
  • Patent number: 9312137
    Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 12, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
  • Publication number: 20150380309
    Abstract: Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor.
    Type: Application
    Filed: June 26, 2014
    Publication date: December 31, 2015
    Inventors: Salil Mujumdar, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, Bin Yang
  • Publication number: 20150118828
    Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Intermolecular Inc.
    Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
  • Publication number: 20150093889
    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a hydrogen-plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicants: Intermolecular, GLOBALFOUNDRIES, Inc.
    Inventors: Bin Yang, Abhijit Pethe, Albert Lee, Amol Joshi, Ashish Bodke, Kevin Kashefi, Salil Mujumdar
  • Publication number: 20150093887
    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a NF3/NH3 plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.
    Type: Application
    Filed: April 15, 2014
    Publication date: April 2, 2015
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Bin Yang, Shurong Liang, Kristina Young-Fisher, Kevin Kashefi, Amol Joshi, Salil Mujumdar, Abhijit Pethe, Albert Lee, Ashish Bodke
  • Publication number: 20150093914
    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate comprising a GeOx layer formed thereon and exposing the semiconductor substrate to first and second atomic layer deposition (ALD) processes. The first ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a first oxygen-containing precursor. The second ALD process includes exposing the semiconductor substrate to a first gaseous precursor comprising aluminum and exposing the semiconductor substrate to a second gaseous precursor comprising a second oxygen-containing precursor.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicants: Intermolecular, GLOBALFOUNDRIES, Inc.
    Inventors: Bin Yang, Abhijit Pethe, Albert Lee, Amol Joshi, Ashish Bodke, Kevin Kashefi, Salil Mujumdar
  • Patent number: 8945414
    Abstract: Oxides (e.g., native or thermal silicon oxide) are etched from underlying silicon with a mixture of fluorine and oxygen radicals generated by a remote plasma. The oxygen radicals rapidly oxidize any uncovered bare silicon areas, preventing the pitting that can result from fluorine etching bare silicon more rapidly than it etches the surrounding oxide. A very thin (few ?), highly uniform passivation layer remaining on the silicon after the process may be left in place or removed. An oxygen-impermeable layer may be formed in-situ immediately afterward to prevent further oxidation. A pre-treatment with oxygen radicals alone fills pores and gaps in the oxide before etching begins.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: February 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Jingang Su, Ashish Bodke, Abhijit Pethe, J Watanabe