Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

Abstract: A storage device that includes a non-volatile memory with a control circuitry is provided. The control circuitry is communicatively coupled to a memory block that includes an array of memory cells. The control circuitry is configured to program one or more bits of data into the memory cells. The control circuitry is further configured to operate the non-volatile memory in a multi-bit per memory cell mode, monitor a usage metric while the non-volatile memory is operating in the multi-bit per memory cell mode, and determine if the usage metric has crossed a predetermined threshold. In response to the usage metric not crossing the predetermined threshold, the control circuitry continues to operate the non-volatile memory in the multi-bit per memory cell mode. In response to the usage metric crossing the predetermined threshold, the control circuitry automatically operates the non-volatile memory in a single-bit per memory cell mode.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

Abstract: Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to different amounts, creating different erase speeds among SC-SGD. SC-SGDs with a greater degree/amount of cut have slower erase speeds as compared to SC-SGDs with a lesser degree/amount of cut. However, verify levels among SC-SGDs can differ to produce SC-SGDs with Vt's such that their erase speeds match with each other as well as with FC-SGD.

Abstract: Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to different amounts, creating different erase speeds among SC-SGD. SC-SGDs with a greater degree/amount of cut have slower erase speeds as compared to SC-SGDs with a lesser degree/amount of cut. However, verify levels among SC-SGDs can differ to produce SC-SGDs with Vt's such that their erase speeds match with each other as well as with FC-SGD.

Abstract: A storage device is provided that conditionally performs read refresh in blocks having higher P/E cycles or older programming times, while refraining from performing read refreshes in blocks having lower P/E cycles or recent programming times. The storage device includes a memory and a controller. The memory includes a block having cells. The controller performs a read refresh on the cells when a number of P/E cycles of the block exceeds an age threshold or after a threshold amount time has elapsed since data was programmed in the block. The controller may also refrain from performing read refreshes on the cells until the number of P/E cycles exceeds the age threshold or until a threshold amount of time has elapsed since the data is programmed. As a result, lower BER may occur due to wider Vt margins, while power and system overhead may be saved.

Abstract: Apparatuses and techniques are described for reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.

Abstract: A reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation.

Abstract: An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program the memory cells and count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data state, the programming circuit applies a plurality of programming pulses at increasing voltage levels and a plurality of verify pulses at a second verify voltage level to the selected word line. During programming of the memory cells to the second programmed data state, the number of verify pulses is one fewer than the number of programming pulses and bitscan operations are skipped.

Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

Abstract: An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program the memory cells and count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data state, the programming circuit applies a plurality of programming pulses at increasing voltage levels and a plurality of verify pulses at a second verify voltage level to the selected word line. During programming of the memory cells to the second programmed data state, the number of verify pulses is one fewer than the number of programming pulses and bitscan operations are skipped.

Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

Abstract: A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit counts an over programming number of the storage elements having a threshold voltage exceeding an over programming verify level of the respective target data state that is less than a default verify level and based on the program step voltage. The control circuit adjusts a voltage of the respective bit line to one or more adjusted levels in response to the over programming number being greater than a predetermined over programming number.

Abstract: A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit counts an over programming number of the storage elements having a threshold voltage exceeding an over programming verify level of the respective target data state that is less than a default verify level and based on the program step voltage. The control circuit adjusts a voltage of the respective bit line to one or more adjusted levels in response to the over programming number being greater than a predetermined over programming number.

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation.

Abstract: An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data state, the programming circuit applies a plurality of programming pulses at increasing voltage levels and a plurality of verify pulses at a second verify voltage level to the selected word line. During programming of the memory cells to the second programmed data state, the number of verify pulses is one fewer than the number of programming pulses.