Patents by Inventor Abhinav Das
Abhinav Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9880842Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.Type: GrantFiled: March 15, 2013Date of Patent: January 30, 2018Assignee: Intel CorporationInventors: Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy, David J. Sager, Jason M. Agron
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Patent number: 9766911Abstract: Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary. Moreover, the product includes program code for fast-forwarding at least one thread so that its state is consistent with the guest instruction boundary.Type: GrantFiled: April 24, 2009Date of Patent: September 19, 2017Assignee: ORACLE AMERICA, INC.Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
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Publication number: 20160285958Abstract: Systems, apparatuses and methods may provide for isolating native information from non-native information, wherein the native information is associated with a mobile application running in a managed runtime environment. Additionally, the native information may be checkpointed and transferred from a first device to a second device in response to a live migration event. In one example, the native information includes native code and native state data and isolating the native information from the non-native information includes dispatching one or more native function calls to a binary translation (BT) container that manages a memory pool dedicated to the native information.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Abhinav Das, Saurabh Shukla, Wei Li, Daniel M. Lavery
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Patent number: 9189233Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.Type: GrantFiled: June 26, 2012Date of Patent: November 17, 2015Assignee: INTEL CORPORATIONInventors: Ruchira Sasanka, Abhinav Das, Jeffrey J. Cook, Jayaram Bobba, Arvind Krishnaswamy, David J. Sager, Suresh Srinivas
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Patent number: 9170789Abstract: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data (“SIMD”) instructions.Type: GrantFiled: March 5, 2013Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Jayaram Bobba, Michael R. Greenfield, Suresh Srinivas
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Publication number: 20140281424Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy, David J. Sager, Jason M. Agron
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Publication number: 20140258677Abstract: Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data (“SIMD”) instructions.Type: ApplicationFiled: March 5, 2013Publication date: September 11, 2014Inventors: Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Jayaram Bobba, Michael R. Greenfield, Suresh Srinivas
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Publication number: 20130262779Abstract: Profiling and analyzing modules may be combined with hardware modules to identify a likelihood that a particular region of code in a computer program contains data that would benefit from prefetching. Those regions of code that would not benefit from prefetching may also be identified. Once a region of code has been identified, a hardware prefetcher may be selectively enabled or disable when executing code in identified code region. In some instances, once a processing device finishes executing code in the identified code region, the state of the hardware prefetcher may then be switched back to its original state. Systems, methods, and media are provided.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventors: Jayaram BOBBA, Ryan CARLSON, Jeffrey Cook, Abhinav DAS, Jason HORIHAN, Wei LI, Suresh SRINIVAS, Sreenivas SUBRAMONEY, Krishnaswamy VISWANATHAN
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Patent number: 8521760Abstract: Techniques for selectively translating resource requests from a program running on a computer system are disclosed. The resource request may be a request to access a file, library file, API, etc. The resource request may be a system call or library call. The computer program may be non-native to the computer system. Translation of resource requests may occur within the operating system or outside it. A resource request containing a reference to a first path and file name may be selectively translated by altering the resource request to contain a reference to a second path and file name. After selectively translating a request, he request is caused to be serviced. A resource request may be serviced by forwarding it to an operating system, and a result may be sent back to the program.Type: GrantFiled: December 30, 2008Date of Patent: August 27, 2013Assignee: Oracle America, Inc.Inventors: Abhinav Das, William Y. Chen, Jiwei Lu, Chandramouli Banerjee
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Publication number: 20130166886Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.Type: ApplicationFiled: June 26, 2012Publication date: June 27, 2013Inventors: Ruchira Sasanka, Abhinav Das, Jeffrey J. Cook, Jayaram Bobba, Arvind Krishnaswamy, David I. Sager, Suresh Srinivas
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Patent number: 8473930Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving the guest executable binary into a computer readable medium. The guest executable binary is executed on the host computer architecture by translating the guest executable binary into a translated executable binary. Each instruction of the translated executed binary is then executed on the host computer architecture. Signals are responded to by placing signal information on a signal queue and deferring signal handling until a safe point is reached. A computer system implementing the method is also provided.Type: GrantFiled: November 5, 2008Date of Patent: June 25, 2013Assignee: Oracle America, Inc.Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
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Patent number: 8346531Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving a guest executable binary encoded on a computer readable medium. The guest executable binary is executable on a first computer architecture. Moreover, the guest executable binary includes a mutex lock encoded instructions for implementing a mutex lock. The guest executable binary is then executed on the host computer architecture by first translating the guest executable binary to a translated executable binary. The encoded instructions for implementing a mutex lock are translated by mapping the mutex lock to an instance of a compound mutex lock data structure. A computer system implementing methods for executing non-native binaries on a host computer architecture is also provided.Type: GrantFiled: November 5, 2008Date of Patent: January 1, 2013Assignee: Oracle America, Inc.Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
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Publication number: 20100274551Abstract: Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary.Type: ApplicationFiled: April 24, 2009Publication date: October 28, 2010Applicant: Sun Microsystems, Inc.Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
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Publication number: 20100169308Abstract: Techniques for selectively translating resource requests from a program running on a computer system are disclosed. The resource request may be a request to access a file, library file, API, etc. The resource request may be a system call or library call. The computer program may be non-native to the computer system. Translation of resource requests may occur within the operating system or outside it. A resource request containing a reference to a first path and file name may be selectively translated by altering the resource request to contain a reference to a second path and file name. After selectively translating a request, he request is caused to be serviced. A resource request may be serviced by forwarding it to an operating system, and a result may be sent back to the program.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Inventors: Abhinav Das, William Y. Chen, Jiwei Lu, Chandramouli Banerjee
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Publication number: 20100114555Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving a guest executable binary encoded on a computer readable medium. The guest executable binary is executable on a first computer architecture. Moreover, the guest executable binary includes a mutex lock encoded instructions for implementing a mutex lock. The guest executable binary is then executed on the host computer architecture by first translating the guest executable binary to a translated executable binary. The encoded instructions for implementing a mutex lock are translated by mapping the mutex lock to an instance of a compound mutex lock data structure. A computer system implementing methods for executing non-native binaries on a host computer architecture is also provided.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee
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Publication number: 20100115497Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving the guest executable binary into a computer readable medium. The guest executable binary is executed on the host computer architecture by translating the guest executable binary into a translated executable binary. Each instruction of the translated executed binary is then executed on the host computer architecture. Signals are responded to by placing signal information on a signal queue and deferring signal handling until a safe point is reached. A computer system implementing the method is also provided.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Applicant: SUN MICROSYSTEMS, INC.Inventors: Abhinav Das, Jiwei Lu, William Y. Chen, Chandramouli Banerjee