Patents by Inventor Abinash ROY
Abinash ROY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055356Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Bharani CHAVA, Abinash ROY, Stanley Seungchul SONG, Jonghae KIM
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Patent number: 11876085Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.Type: GrantFiled: June 25, 2021Date of Patent: January 16, 2024Assignee: QUALCOMM INCORPORATEDInventors: Abinash Roy, Lohith Kumar Vemula, Bharani Chava, Jonghae Kim
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Publication number: 20230387077Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The first power interconnect includes a first power plane. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The second power interconnect includes a second power plane. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.Type: ApplicationFiled: August 3, 2023Publication date: November 30, 2023Inventors: Bharani CHAVA, Abinash ROY
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Patent number: 11830819Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.Type: GrantFiled: June 24, 2021Date of Patent: November 28, 2023Assignee: QUALCOMM INCORPORATEDInventors: Bharani Chava, Abinash Roy, Stanley Seungchul Song, Jonghae Kim
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Patent number: 11764186Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.Type: GrantFiled: January 29, 2021Date of Patent: September 19, 2023Assignee: QUALCOMM INCORPORATEDInventors: Bharani Chava, Abinash Roy
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Publication number: 20220415808Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Bharani CHAVA, Abinash ROY, Stanley Seungchul SONG, Jonghae KIM
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Publication number: 20220415868Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Abinash ROY, Lohith Kumar VEMULA, Bharani CHAVA, Jonghae KIM
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Patent number: 11515289Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.Type: GrantFiled: September 9, 2020Date of Patent: November 29, 2022Assignee: QUALCOMM IncorporatedInventors: Bharani Chava, Stanley Seungchul Song, Abinash Roy, Jonghae Kim
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Patent number: 11430797Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.Type: GrantFiled: June 30, 2020Date of Patent: August 30, 2022Assignee: QUALCOMM IncorporatedInventors: Abinash Roy, Bharani Chava
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Publication number: 20220246580Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventors: Bharani CHAVA, Abinash ROY
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Publication number: 20220077109Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Bharani CHAVA, Stanley Seungchul SONG, Abinash ROY, Jonghae KIM
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Patent number: 11249530Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.Type: GrantFiled: November 25, 2020Date of Patent: February 15, 2022Assignee: QUALCOMM INCORPORATEDInventors: Dipti Ranjan Pal, Harshat Pant, Abinash Roy, Shih-Hsin Jason Hu, Keith Alan Bowman
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Publication number: 20210408015Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Inventors: Abinash ROY, Bharani CHAVA
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Patent number: 10915157Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.Type: GrantFiled: February 14, 2019Date of Patent: February 9, 2021Assignee: QUALCOMM IncorporatedInventors: Dipti Ranjan Pal, Jeffrey Gemar, Abinash Roy
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Publication number: 20200264682Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.Type: ApplicationFiled: February 14, 2019Publication date: August 20, 2020Inventors: Dipti Ranjan PAL, Jeffrey GEMAR, Abinash ROY
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Patent number: 10732697Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.Type: GrantFiled: May 14, 2018Date of Patent: August 4, 2020Assignee: QUALCOMM IncorporatedInventors: Raghavendra Srinivas, Abhijit Joshi, Bharat Kavala, Abinash Roy
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Publication number: 20200019229Abstract: Systems and methods for power sequencing include, for an integrated circuit comprising one or more logic instances, one or more power multiplexers to select from at least a first power rail and a second power rail, an active power rail to supply power to the one or more logic instances. One or more sequence multiplexers are used to choose from at least a first power sequence for the first power rail and a second power sequence for the second power rail, an active power sequence. One or more head switches coupled to the one or more logic instances are either turned on, in the active power sequence, to supply power to the one or more logic instances from the active power rail, or turned off, in the active power sequence, the one or more head switches, to power down the one or more logic instances.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Raghavendra SRINIVAS, Abhijit JOSHI, Bharat KAVALA, Abinash ROY
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Publication number: 20190346908Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: Raghavendra SRINIVAS, Abhijit JOSHI, Bharat KAVALA, Abinash ROY
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Publication number: 20190339757Abstract: Methods and apparatuses to power up multiple load circuits are presented. The apparatus includes a power delivery network, multiple load circuits configured to be powered via the power delivery network, and a wakeup control circuit configured to power up the multiple load circuits at a frequency based on a resonance frequency of the power delivery network. The method includes delivering power to the multiple load circuits by a power source via a power delivery network and powering up the multiple load circuits at a frequency, by a wakeup control circuit, based on a resonance frequency of the power delivery network.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventors: Abinash ROY, Dipti Ranjan PAL, Avinash GADDE