Patents by Inventor Abishek Manian
Abishek Manian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137198Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.Type: ApplicationFiled: April 27, 2023Publication date: April 25, 2024Inventors: Abishek MANIAN, Ashkan ROSHAN ZAMIR, Yonghui TANG, Robin GUPTA, Michael G. VRAZEL
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Publication number: 20240113713Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Inventors: Nithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
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Patent number: 11916703Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.Type: GrantFiled: December 14, 2022Date of Patent: February 27, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Nithin Sathisan Poduval, Roland Nii Ofei Ribeiro
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Patent number: 11888478Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.Type: GrantFiled: October 29, 2021Date of Patent: January 30, 2024Assignee: Texas Instruments IncorporatedInventors: Nithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
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Patent number: 11743080Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.Type: GrantFiled: October 28, 2020Date of Patent: August 29, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Amit Rane, Ashwin Kottilvalappil Vijayan
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Publication number: 20230246884Abstract: Systems, circuitry and methods correct baseline wander while reducing amplitude difference between the input signal to a data sampler and the output signal of an output-swing-controlled buffer. Example baseline wander correction circuitry comprises a baseline wander correction loop that receives an equalized data signal, a feedback signal and a buffer control signal, and corrects baseline wander in the data sampler input signal. Baseline wander correction loop generates the buffer output signal based on the data sampler output signal and the buffer control signal. Baseline wander correction circuitry also comprises a feedback circuit that receives the data sampler output signal and generates the feedback signal, and an amplitude estimation loop that receives the data sampler input and output signals and outputs the buffer control signal to control the peak-to-peak swing of the buffer output signal.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Abishek Manian, Amit Rane
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Publication number: 20230135422Abstract: An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Nithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
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Publication number: 20230122240Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.Type: ApplicationFiled: December 14, 2022Publication date: April 20, 2023Inventors: Abishek MANIAN, Nithin Sathisan PODUVAL, Roland Nii Ofei RIBEIRO
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Patent number: 11621715Abstract: Systems, circuitry and methods measure data transition metrics of incoming data, average the measurements of each metric at a set time interval for multiple intervals to generate multiple averaged values, and select a maximum of the multiple averaged values for each metric. The maximum values of each measurement cycle are compared with corresponding multiple thresholds defining respective ranges, and the outputs are used by a state machine to determine an equalization level and the rate of the incoming data. When the thresholds are not met, the state machine adjusts the equalization level, and when a sub-rate is detected using a third threshold for one of the metrics, the clock rate is also adjusted. Locking of a clock and data recovery (CDR) circuit is attempted when the maximum values for each metric are within their respective ranges.Type: GrantFiled: January 11, 2022Date of Patent: April 4, 2023Assignee: Texas Instruments IncorporatedInventors: Robin Gupta, Abishek Manian
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Patent number: 11575546Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.Type: GrantFiled: March 5, 2021Date of Patent: February 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Nithin Sathisan Poduval, Roland Nii Ofei Ribeiro
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Patent number: 11539555Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.Type: GrantFiled: November 12, 2020Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Ashwin Kottilvalappil Vijayan, Amit Rane, Ashkan Roshan Zamir
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Publication number: 20220286327Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Inventors: Abishek MANIAN, Nithin Sathisan PODUVAL, Roland Nii Ofei RIBEIRO
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Patent number: 11323109Abstract: A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.Type: GrantFiled: October 30, 2020Date of Patent: May 3, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Surya Theja Golakonda, Robin Gupta
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Patent number: 11239834Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.Type: GrantFiled: December 11, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Abishek Manian
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Publication number: 20210409246Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.Type: ApplicationFiled: November 12, 2020Publication date: December 30, 2021Inventors: Abishek MANIAN, Ashwin Kottilvalappil VIJAYAN, Amit RANE, Ashkan ROSHAN ZAMIR
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Publication number: 20210409248Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.Type: ApplicationFiled: October 28, 2020Publication date: December 30, 2021Inventors: Abishek MANIAN, Amit RANE, Ashwin Kottilvalappil VIJAYAN
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Publication number: 20210409014Abstract: A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.Type: ApplicationFiled: October 30, 2020Publication date: December 30, 2021Inventors: Abishek MANIAN, Surya Theja GOLAKONDA, Robin GUPTA
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Publication number: 20210152165Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.Type: ApplicationFiled: December 11, 2020Publication date: May 20, 2021Inventor: Abishek MANIAN
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Patent number: 10897245Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.Type: GrantFiled: November 18, 2019Date of Patent: January 19, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Abishek Manian
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Patent number: 10873444Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.Type: GrantFiled: March 27, 2020Date of Patent: December 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abishek Manian, Michael Gerald Vrazel