Abstract: Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.

Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.

Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.

Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.

Abstract: Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.

Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.

Abstract: A method of forming a semiconductor structure includes, in a radio frequency (RF) deposition chamber, depositing a titanium film using physical vapor deposition and forming a graded hard mask film by reactive sputtering the titanium film with nitrogen in the RF deposition chamber. The graded hard mask film is a titanium nitride film with a graded vertical concentration of nitrogen. The method may further include, during deposition of the titanium film and during formation of the graded hard mask film, modulating one or more parameters of the RF deposition chamber, such as modulating an auto capacitance tuner (ACT) current, modulating the RF power, and modulating the pressure of the RF deposition chamber.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: A method of forming a semiconductor structure includes, in a radio frequency (RF) deposition chamber, depositing a titanium film using physical vapor deposition and forming a graded hard mask film by reactive sputtering the titanium film with nitrogen in the RF deposition chamber. The graded hard mask film is a titanium nitride film with a graded vertical concentration of nitrogen. The method may further include, during deposition of the titanium film and during formation of the graded hard mask film, modulating one or more parameters of the RF deposition chamber, such as modulating an auto capacitance tuner (ACT) current, modulating the RF power, and modulating the pressure of the RF deposition chamber.

Abstract: Embodiments describing an approach for creating an etch resistant Titanium Oxide film for sidewall image transfer (SIT) spacer application. Generating a mandrel formation, and depositing a Titanium Oxide spacer on the mandrel formation, wherein depositing the Titanium Oxide spacer further comprises at least one of exposing the Titanium Oxide spacer to at least 100 C or plasma conditions of RF power are at least 500 W for at least 1 second.

Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.

Abstract: Embodiments describing an approach for creating an etch resistant Titanium Oxide film for sidewall image transfer (SIT) spacer application. Generating a mandrel formation, and depositing a Titanium Oxide spacer on the mandrel formation, wherein depositing the Titanium Oxide spacer further comprises at least one of exposing the Titanium Oxide spacer to at least 100 C or plasma conditions of RF power are at least 500 W for at least 1 second.

Abstract: Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures.

Abstract: Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures.

Abstract: Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures.

Abstract: An organic planarization layer (OPL) is formed above a functional layer located on a substrate. A titanium-oxide layer is formed above the OPL, wherein forming the titanium-oxide layer comprises titanium, oxide, carbon, and nitrogen. A photoresist layer is patterned above a first portion of the titanium-oxide layer. A second portion of the titanium-oxide layer is removed using a wet stripping technique. The photoresist layer and the OPL are removed using a dry etch technique, wherein the first portion of the titanium-oxide layer remains over a remaining portion of the OPL. The first portion of the titanium-oxide layer and the functional layer are removed using the wet stripping technique. The remaining portion of the OPL is removed using a dry stripping technique.