Abstract: Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract: Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives.

Abstract: A Universal Serial Bus (USB) memory card includes a tube metal housing that is rectangularly-shaped and a Chip-On-Board (COB)-Universal Serial Bus (USB) device and a carrier substrate having a U-block disposed on one side of thereof and vertically extending upwardly from a bottom surface of the U-block, the COB-USB device positioned on the carrier substrate forming a USB card sub-assembly, the USB card sub-assembly being securely located inside the metal housing with the U-block serving to stop the COB-USB device from slipping out of the metal housing.

Abstract: High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically.

Abstract: Solid state drive (SSD) testing processes and methods are disclosed.

Abstract: In an embodiment of the present invention, a memory card includes a bottom plastic piece having a plurality of lateral sides, one of which includes a notch, and a cavity interposed along the lateral sides. A printed circuit board (PCB) assembly, including memory, is positioned in the cavity. A fin-structure is created as part of the manufacturing process of the bottom plastic piece of the card. The memory card is configured to function in a read-write mode when the fin-structure is present, and in a write-protect mode when the fins are snapped off, and the notch is exposed. Alternatively, a plug device can be insertably positioned into the notch, causing the memory card to function in a read-write mode when the plug device is positioned into the notch, and in a write-protect mode when the plug device is removed and the notch is exposed.

Abstract: Data error detection and correction in non-volatile memory devices are disclosed. Data error detection and correction can be performed with software, hardware or a combination of both. Generally an error corrector is referred to as an ECC (error correction code). One of the most relevant codes using in non-volatile memory devices is based on BCH (Bose, Ray-Chaudhuri, Hocquenghem) code. In order to correct reasonable number (e.g., up to 8-bit (eight-bit)) of random errors in a chunk of data (e.g., a codeword of 4200-bit with 4096-bit information data), a BCH(4200,4096,8) is used in GF(213). ECC comprises encoder and decoder. The decoder further comprises a plurality of error detectors and one error corrector. The plurality of error decoders is configured for calculating odd terms of syndrome polynomial for multiple channels in parallel, while the error corrector is configured for sequentially calculating even terms of syndrome polynomial, key solver and error location.

Abstract: High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.

Abstract: A secured digital (SD) card including a bottom plastic piece having a plurality of lateral sides, said bottom plastic piece further having a cavity interposed along said plurality of lateral sides, in accordance with an embodiment of the present invention. The SD card further having a top cover and a printed circuit board (PCB) assembly positioned in said cavity, said top cover for covering said PCB assembly inside said cavity, one of said plurality of lateral sides of said bottom plastic piece having a notch, said SD card further having a male guide insertably positioned inside said notch, said SD card further having a female switch clamped onto said male guide to form a write-protect switch.

Abstract: Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.

Abstract: A molded secured digital (SD) card having a bottom plastic piece having a plurality of lateral sides, said bottom plastic piece further having a cavity interposed along said plurality of lateral sides, in accordance with an embodiment of the present invention. The molded SD card further having a printed circuit board (PCB) assembly positioned in said cavity, one of said plurality of lateral sides of said bottom plastic piece having a notch recess, said molded SD card further having a male guide insertably positioned into said notch recess, said molded SD card further having a female switch clamped onto said male guide to form a write-protect switch.

Abstract: A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end and a swivel cap having a side slit that serves as an opening into which the slim USB device travels horizontally, the side slit being disposed along a lateral side of the swivel cap. The USB flash drive also includes a USB device rivet placed into the slim USB device and the swivel cap to pivotally connect them at one of the ends of the slim USB device, so that the slim USB device is pivotally extendable outwardly from the side slit in a closed or open position. The swivel rocker is pivotally extendable outwardly from the opposite end of the slim USB device and when the swivel rocker is extended outwardly, the slim USB device is caused to extend outwardly.

Abstract: A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs.

Abstract: Thin solid state drive (SSD) housing structures are described. According to one embodiment of the invention, a structure for housing an SSD includes a pair of brackets configured to support a PCBA of the SSD at either side of the PCBA via one or more ledges with corresponding fastener holes pre-configured thereon. The ledges are attached to inside surface of the brackets. Each of the brackets has a slab shape with a length and a height. The length is parallel to horizontal direction, while the height parallel to vertical. The ledges are located at mid-height and orientated substantially perpendicular to the brackets such that the PCBA is supported horizontally. In order to securely connect the PCBA with the brackets, a plurality of metal fasteners is used. The fasteners are placed through the fastener holes on the ledges and through corresponding alignment holes pre-configured on the PCBA.