Abstract: A system and method for operation of cross-platform applications on a wireless phone is provided. The applications can be cross-platform applications in that the same application code can be run on different wireless phone platforms. The method and system can for a wireless phone which runs a cross-platform application that enables the processor of the wireless phone to run the cross-platform applications. The wireless phone processor can operate to determine platform parameters of the phone and then run the cross-platform application using the determined phone parameters.

Abstract: A system and method for operation of cross-platform applications on a wireless phone is provided. The applications can be cross-platform applications in that the same application code can be run on different wireless phone platforms. The method and system can for a wireless phone which runs a cross-platform application that enables the processor of the wireless phone to run the cross-platform applications. The wireless phone processor can operate to determine platform parameters of the phone and then run the cross-platform application using the determined phone parameters.

Abstract: A system and method for operation of cross-platform applications on a wireless phone is provided. The applications can be cross-platform applications in that the same application code can be run on different wireless phone platforms. The method and system can for a wireless phone which runs a cross-platform application that enables the processor of the wireless phone to run the cross-platform applications. The wireless phone processor can operate to determine platform parameters of the phone and then run the cross-platform application using the determined phone parameters.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: An efficient polling technique to attain improved system performance preserves the concept of polling, but instead of polling across system buses to the device, a poll is made within the processor's cache structure, which is typically internal to the processor complex or attached on a local isolated bus. The polling status location is mapped in the cachable address space of the processor. Hence, the polling occurs to a normal cachable location. When the device completes its task, it signals to the polling loop by invalidating the cache line corresponding to the poll location. The next time software tries to read the status value, the processor misses in its cache and automatically reloads the updated status value from the device. This causes the polling loop to exit and normal processing continues. The only bus traffic that results is that which is issued by the device to signal cache line invalidation and a subsequent processor initiated cache line reload.

Abstract: A method for rendering pixels for an object to be displayed in an image, based on parameters defining the object, by generating, in parallel, pixel values for at least some pixels contained in the object, but fewer than all pixels in an image, and repeating that step until all pixels for the object have been rendered.

Abstract: A method and apparatus creates a display of a scene having a plurality of object elements. One or more frame buffers are utilized in creating the display.

Abstract: A system for the storage, retrieval and manipulation of significantly large amounts of data to produce highly complex and visually pleasing graphics within the time constraint of a full motion video raster scanning system by storing memory data corresponding to each of the individual object elements to be displayed over a period of time, storing lists of identification and display instruction data with respect to those object elements, selecting desired identification and display instruction data for selected display elements appropriate to a particular instant of time and placing such selected data into an appropriate memory, and then creating, from those selected instructions and from the stored data relating to the selected object elements, display data which, in real time, produces the desired display. The initially stored identification and display instructions are preferably in the form of a linked list with the items in each list arranged in order of desired visible priority.

Abstract: A system for the storage, retrieval and manipulation of data for producing a display, in which inter alia, color availability is in the form of appropriately pre-selected palettes, three-dimensional or planar objects are composed of patterns or elements which are individually stored, the display image is made up in buffers which alternate as construction and display buffers by data accessed in memory by lists linking them in ascending order of visible priority, the data then being written into the buffers, the nature of the data storage varying in predetermined fashion for different types of objects, all so that highly complex and visually pleasing graphics can be displayed and manipulated within the time constraint of a full motion video raster scanning system.