Abstract: Described examples include, an integrated circuit package having a die with a surface and at least two bond pads in the first surface. The integrated circuit package also includes at least two leads having a first portion and a second portion, the die coupled to the first portion and the at least two bond pads having a conductive connection the leads, the first portion of the at least two leads having a first width greater than a second width of the second portion. The integrated circuit package also including an encapsulation covering the die and the first portion of the at least two leads, the second portion of the at least two leads extending outside of the encapsulation such that a surface of the second portion is parallel with a surface of the encapsulation and the second portion extends beyond the encapsulation less than a thickness of the encapsulation.

Abstract: Stacked semiconductor chip package system vertical interconnects and related methods are disclosed. A preferred embodiment of the invention includes a first semiconductor chip with a surface bearing a plurality of first fusible metallic coupling elements. A second semiconductor chip has a plurality of second fusible metallic coupling elements. The first and second fusible metallic coupling elements correspond at the adjoining surfaces of the first and second semiconductor chips when stacked, and are fused to form a gold-tin eutectic alloy fused metallic coupling vertically interconnecting the stacked chips.