Abstract: In a microprocessor with a reset circuit arrangement acting in dependence upon the inception of its supply voltage, safe operation is ensured after stoppages or operating voltage interruptions, particularly in view of a delay of the internal program flow up to the orderly start of a quartz-stabilized oscillator in the stationary operation. A reset signal derived from the supply voltage is conducted through a switching stage steadily to the reset input of the microprocessor, which is deactivatable in dependence upon the start of the oscillator contained in the microprocessor so that the reset input is no longer controlled during the steady-state operation. The switching stage, designed as an external microprocessor circuit, is preferably controlled through a voltage booster circuit as normally provided in clock microprocessors for controlling a digital display, and which is supplied through the divided oscillator frequency.