Abstract: A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool.

Abstract: A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.

Abstract: A circuit includes a voltage supply net, a first capacitor connected between the voltage supply net and a reference potential via a first transistor, and a second capacitor connected between the voltage supply net and the reference potential via a second transistor, such that the first and the second capacitor form at least a part of a support capacitance for the voltage supply net. The circuit is configured to provide control signals to control terminals of the first and second transistor such that the first transistor allows for a limited current flow in case of a shortage of the first capacitor and such that the second transistor allows for a limited current flow in case of a shortage of the second capacitor.

Abstract: One embodiment of the invention provides an adapter card for connection to a data bus in a data processing unit. The adapter includes a DDR interface for connection of a DDR memory module, a memory unit for storing test mode data, a switching device, which, in a first switching state, connects the data bus to the DDR interface and, in a second switching state, decouples the DDR interface from the data bus and connects the memory unit to the DDR interface such that test mode data may be transmitted to a connected DDR memory module to call up a test mode in the DDR memory module. The adapter also includes a control circuit with a trigger input to control the switching device between the switching states depending on a trigger signal.

Abstract: A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool.

Abstract: A storage device comprises a storage location, an interface coupled to the storage location, and a data conversion circuit coupled to the storage location and to the interface. The interface is configured for an exchange of data between the storage device and external circuitry coupled to the interface. The data conversion circuit is configured for converting data from a first data format to a second data format. The data conversion circuit is configured to convert at least one of data read from the storage location before they are transferred to the interface, and data received via the interface before they are written to the storage location.

Abstract: A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.

Abstract: An apparatus, method and system for comparing sample data with comparison date is disclosed. One embodiment provides a plurality of storage locations, an interface coupled to a plurality of storage locations for an exchange of data between the plurality of storage locations and external circuitry coupled to the interface, and a data comparator for comparing comparison data stored in the plurality of storage locations and sample data.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: One embodiment of the invention provides an adapter card for connection to a data bus in a data processing unit. The adapter includes a DDR interface for connection of a DDR memory module, a memory unit for storing test mode data, a switching device, which, in a first switching state, connects the data bus to the DDR interface and, in a second switching state, decouples the DDR interface from the data bus and connects the memory unit to the DDR interface such that test mode data may be transmitted to a connected DDR memory module to call up a test mode in the DDR memory module. The adapter also includes a control circuit with a trigger input to control the switching device between the switching states depending on a trigger signal.

Abstract: A method and an apparatus for testing an SDRAM are described. The SDRAM is used as a main memory in the PC, and an additional circuit configuration is accommodated on a plug-in board and has an additional memory in the form of an SRAM and logic circuits. The method according to the invention allows the SDRAM to be tested in a module bank in the running PC to be set deliberately to a test mode. In this case the code for test mode activation is modified by a high-level language program (PASCAL) in accordance with the user requirements, is copied to the additional memory on the plug-in board, and is then called by the high-level language program using MS DOS. After activation of the selected test mode by a code programmed in Assembler, a defined jump is made back to the calling program once again. This allows the use of the test mode provided in the SDRAM in standard PCs and using standard operating systems. This greatly increases the test options for SDRAMs on standard PCs.

Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

Abstract: A method and an apparatus for testing an SDRAM are described. The SDRAM is used as a main memory in the PC, and an additional circuit configuration is accommodated on a plug-in board and has an additional memory in the form of an SRAM and logic circuits. The method according to the invention allows the SDRAM to be tested in a module bank in the running PC to be set deliberately to a test mode. In this case the code for test mode activation is modified by a high-level language program (PASCAL) in accordance with the user requirements, is copied to the additional memory on the plug-in board, and is then called by the high-level language program using MS DOS. After activation of the selected test mode by a code programmed in Assembler, a defined jump is made back to the calling program once again. This allows the use of the test mode provided in the SDRAM in standard PCs and using standard operating systems. This greatly increases the test options for SDRAMs on standard PCs.