Patents by Inventor Adalberto G. Yanes
Adalberto G. Yanes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11086565Abstract: A computer-implemented method, according to one embodiment, includes: receiving a stream of data, and selecting more than one block of memory to write the stream of data to. The selected blocks of memory are in a memory that includes a plurality of blocks. Moreover, the data is written across the selected blocks of memory in parallel. The blocks of memory are also selected such that no two or more of the selected blocks of memory have an effect on a read apparent voltage of a same one of the plurality of blocks in the memory. Other systems, methods, and computer program products are described in additional embodiments.Type: GrantFiled: October 1, 2018Date of Patent: August 10, 2021Assignee: International Business Machines CorporationInventors: Kevin E. Sallese, Timothy J. Fisher, Adalberto G. Yanes, Jason Szecheong Ma, Charles A. Keller, Aaron D. Fry, Van Huynh, Nikolaos Papandreou
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Patent number: 10770155Abstract: Read Apparent Voltage (RAV) is an anomality in which an apparent threshold voltage of a storage cell transistor does not equal the actual threshold voltage of that same transistor by a large enough magnitude that the binary state of transistor is not read correctly. An infector page may cause the RAV anomality within a different infected page. To determine whether any page is an infector, each page is programmed, a page within each block is read, an acting infector page within an acting infector block is set, a possible infected page within a possible infected block is set, the acting infector page is read a predetermined plurality of instances, the possible infected page is read, a raw bit error rate (RBER) of the read of the possible infected page is determined, and the acting infector page is set as an actual infector page based upon the determined RBER.Type: GrantFiled: October 11, 2018Date of Patent: September 8, 2020Assignee: International Business Machines CorporationInventors: Timothy Fisher, Aaron D. Fry, Van Huynh, Charles A. Keller, Jason Szecheong Ma, Kevin E. Sallese, Adalberto G. Yanes
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Publication number: 20200117371Abstract: Read Apparent Voltage (RAV) is an anomality in which an apparent threshold voltage of a storage cell transistor does not equal the actual threshold voltage of that same transistor by a large enough magnitude that the binary state of transistor is not read correctly. An infector page may cause the RAV anomality within a different infected page. To determine whether any page is an infector, each page is programmed, a page within each block is read, an acting infector page within an acting infector block is set, a possible infected page within a possible infected block is set, the acting infector page is read a predetermined plurality of instances, the possible infected page is read, a raw bit error rate (RBER) of the read of the possible infected page is determined, and the acting infector page is set as an actual infector page based upon the determined RBER.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Inventors: Timothy Fisher, Aaron D. Fry, Van Huynh, Charles A. Keller, Jason Szecheong Ma, Kevin E. Sallese, Adalberto G. Yanes
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Publication number: 20200104071Abstract: A computer-implemented method, according to one embodiment, includes: receiving a stream of data, and selecting more than one block of memory to write the stream of data to. The selected blocks of memory are in a memory that includes a plurality of blocks. Moreover, the data is written across the selected blocks of memory in parallel. The blocks of memory are also selected such that no two or more of the selected blocks of memory have an effect on a read apparent voltage of a same one of the plurality of blocks in the memory. Other systems, methods, and computer program products are described in additional embodiments.Type: ApplicationFiled: October 1, 2018Publication date: April 2, 2020Inventors: Kevin E. Sallese, Timothy J. Fisher, Adalberto G. Yanes, Jason Szecheong Ma, Charles A. Keller, Aaron D. Fry, Van Huynh, Nikolaos Papandreou
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Patent number: 10489086Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.Type: GrantFiled: May 2, 2018Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Adalberto G. Yanes, Timothy Fisher, Charles A. Keller, Jason S. Ma, Kevin E. Sallese, Aaron D. Fry, Van Huynh, Nikolaos Papandreou
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Publication number: 20190339902Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.Type: ApplicationFiled: May 2, 2018Publication date: November 7, 2019Inventors: ADALBERTO G. YANES, TIMOTHY FISHER, CHARLES A. KELLER, JASON S. MA, KEVIN E. SALLESE, AARON D. FRY, VAN HUYNH, NIKOLAOS PAPANDREOU
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Patent number: 10229076Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.Type: GrantFiled: September 9, 2015Date of Patent: March 12, 2019Assignee: International Business Machines CorporationInventors: Eric N. Lais, Adalberto G. Yanes
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Patent number: 10133694Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.Type: GrantFiled: September 29, 2015Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Eric N. Lais, Adalberto G. Yanes
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Patent number: 9971517Abstract: A method, according to one embodiment, includes: receiving a recirculation command; performing a coarse page lookup to determine valid ones of logical pages to be recirculated; requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages; and sending write commands corresponding to verified valid logical pages from the fine page lookup. Other systems, methods, and computer program products are described in additional embodiments.Type: GrantFiled: March 22, 2017Date of Patent: May 15, 2018Assignee: International Business Machines CorporationInventors: Timothy J. Fisher, Lincoln T. Simmons, Adalberto G. Yanes
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Patent number: 9946594Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: GrantFiled: August 19, 2015Date of Patent: April 17, 2018Assignee: International Business Machines CorporationInventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
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Patent number: 9875153Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: GrantFiled: January 18, 2017Date of Patent: January 23, 2018Assignee: International Business Machines CorporationInventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
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Patent number: 9811419Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: GrantFiled: January 18, 2017Date of Patent: November 7, 2017Assignee: International Business Machines CorporationInventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
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Publication number: 20170192677Abstract: A method, according to one embodiment, includes: receiving a recirculation command; performing a coarse page lookup to determine valid ones of logical pages to be recirculated; requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages; and sending write commands corresponding to verified valid logical pages from the fine page lookup. Other systems, methods, and computer program products are described in additional embodiments.Type: ApplicationFiled: March 22, 2017Publication date: July 6, 2017Inventors: Timothy J. Fisher, Lincoln T. Simmons, Adalberto G. Yanes
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Patent number: 9652157Abstract: A method, according to one embodiment, includes: receiving a recirculation command, performing a coarse page lookup to determine valid ones of logical pages to be recirculated, issuing write commands for the valid logical pages, requesting performance of a fine page lookup on source physical addresses containing the valid logical pages to verify the valid logical pages, receiving verified valid logical pages resulting from the fine page lookup, and sending the write commands corresponding to the verified valid logical pages. Other systems, methods, and computer program products are described in additional embodiments.Type: GrantFiled: March 19, 2015Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Timothy J. Fisher, Lincoln T. Simmons, Adalberto G. Yanes
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Publication number: 20170123895Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
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Publication number: 20170123893Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
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Publication number: 20170068626Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.Type: ApplicationFiled: September 9, 2015Publication date: March 9, 2017Inventors: Eric N. LAIS, Adalberto G. YANES
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Publication number: 20170068637Abstract: Embodiments of the present disclosure use vendor defined messages (VDMs) to send high priority information (e.g., cache writebacks) on a designated channel that is separate from a channel used for other commands (e.g., normal memory write commands). By using VDMs and a designated channel to send cache writebacks, the cache writebacks will not be blocked by normal memory write commands. For example, an endpoint device may encode cache writebacks as VDMs to be sent to a root complex. The root complex may store the VDMs in a dedicated VDM buffer and send the VDMs on a dedicated VDM channel.Type: ApplicationFiled: September 29, 2015Publication date: March 9, 2017Inventors: Eric N. LAIS, Adalberto G. YANES
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Publication number: 20170052844Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: ApplicationFiled: August 19, 2015Publication date: February 23, 2017Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
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Patent number: 9483350Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.Type: GrantFiled: February 3, 2016Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes