Abstract: A system and method for building a test case operable to test a circuit design, the test case including a summary of instructions. In one embodiment, an instruction generation engine generates a set of instructions of which at least one instruction includes a temporarily uncommitted value. A first summary generation engine portion generates an interfaceable enumeration of the set of instructions wherein each of the temporarily uncommitted values is denoted by an uncommitted reference. A second summary generation engine portion resolves the respective values of the uncommitted references and generates an interfaceable listing of the uncommitted references and their the respective values. The set of instructions and the interfaceable listing of the resolved uncommitted references may be arranged to form the test case.

Abstract: Systems, methods and software products are provided for transaction logging and intelligent error reporting in an expectation-based memory agent checker. Simulation status information is appended to one or more transaction log messages generated by the expectation-based memory agent checker. A cause of error indicated by mismatch between simulated output transaction events and expected output transaction events is determined. Information about the error is appended to one or more error messages generated by the expectation-based memory agent checker.