Abstract: A system, method, and computer program product are provided for allocating processor resources to process compute workloads and graphics workloads substantially simultaneously. The method includes the steps of allocating a plurality of processing units to process tasks associated with a graphics pipeline, receiving a request to allocate at least one processing unit in the plurality of processing units to process tasks associated with a compute pipeline, and reallocating the at least one processing unit to process tasks associated with the compute pipeline.

Abstract: A system, method, and computer program product are provided for allocating processor resources to process compute workloads and graphics workloads substantially simultaneously. The method includes the steps of allocating a plurality of processing units to process tasks associated with a graphics pipeline, receiving a request to allocate at least one processing unit in the plurality of processing units to process tasks associated with a compute pipeline, and reallocating the at least one processing unit to process tasks associated with the compute pipeline.

Abstract: One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.

Abstract: Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

Abstract: Prescient cache management methods and systems are disclosed. In one embodiment, a local cache that operates within a raster engine operations stage of a graphics rendering pipeline is managed by following a number of caching decisions related to a number of cached tiles. Each of these cached tiles has a certain priority to remain in the local cache, with the priority corresponding to a conflict type received from a buffer operating within a pre-raster engine operations stage of the graphics rendering pipeline.

Abstract: Prescient cache management methods and systems are disclosed. In one embodiment, within a pre-raster engine operations stage in a graphics rendering pipeline, tile entries are stored in a buffer. Each of these tile entries is related a transaction request that enters the pre-raster engine operations stage and has a screen coordinates field and a conflict field. If this buffer includes a first tile entry, which is related to a first transaction request associated with a first tile, and a second tile entry, which is related to a second transaction request that enters the pre-raster engine operations stage after the first transaction request and is also associated with the first tile, the conflict field of the first tile entry is updated with a conflict type that reflects a number of tile entries between the first tile entry and the second tile entry.