Patents by Inventor Adam D. Johnson
Adam D. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11952887Abstract: A plunger lift system, as well as a method for monitoring plunger parameters within a wellbore using such a plunger lift system, are provided. The plunger lift system includes a lubricator attached to a wellhead at the surface and a plunger dimensioned to travel through the production tubing upon being released from the lubricator. The plunger lift system also includes magnetic sensor systems installed along the production tubing, where each magnetic sensor system includes a magnetic sensor for detecting the passage of the plunger as it travels through the production tubing, as well a communication device for transmitting communication signals between the magnetic sensor systems and a computing system located at the surface, where the computing system includes a processor and a non-transitory, computer-readable storage medium including computer-executable instructions that direct the processor to dynamically determine the plunger position and/or velocity based on the received communication signals.Type: GrantFiled: April 12, 2022Date of Patent: April 9, 2024Assignee: ExxonMobil Technology and Engineering CompanyInventors: Michael C. Romer, Michael C. Tschauner, Christopher C. Frazier, Andrew D. McFadden, Salvador G. Vela, III, Billy-Bob K. Walker, Adam J. Johnson
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Patent number: 11933221Abstract: A gas turbine engine including a core having a compressor section fluidly connected to a combustor via a primary flowpath and a turbine section connected to the combustor via the core flow path. An assembly is disposed within the gas turbine engine and includes a first part connected to a second part via a radial stack joint. The first part includes a radially inward facing surface contacting a corresponding radially outward facing surface of the second part. A fastener protrudes through the first part and the second part and is configured to maintain the relative positions of the first part and the second part. A channel is disposed on at least one of the radially inward facing surfaces and is positioned between the fastener and a circumferential edge of the first part. The channel is connected to at least one cooling air source.Type: GrantFiled: October 17, 2022Date of Patent: March 19, 2024Assignee: RTX CorporationInventors: Corey D. Anderson, Edward Boucher, Rebecca R. Dunnigan, Nicholas Broulidakis, Matthew Murakami, Daniel R. Brandt, Konrad Kuc, Victoria M. Imlach, Sushruth G. Kamath, Manuel A. Casares Rivas, Eric G. Leamon, Adam Castles, Edmond Cheung, Kyra A. Thole-Wilson, Javier Nebero Johnson
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Patent number: 11921299Abstract: A display system includes a display panel configured to emit a polarized image light having a first polarization state and at least one emission spectrum having a full width at half maxima (FWHM). The display system includes a reflective polarizer configured to receive and reflect the polarized image light as a first reflected polarized image light. For a first light incident at a first predetermined angle, the reflective polarizer has an average reflectance of greater than about 60% across the at least one emission spectrum for the first polarization state, a transmittance of at least about 50% for at least wavelength outside the FWHM of the at least one emission spectrum for the first polarization state, and an average total transmittance of greater than about 70% across a visible wavelength range including the FWHM of the at least one emission spectrum for an orthogonal second polarization state.Type: GrantFiled: November 23, 2021Date of Patent: March 5, 2024Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Adam D. Haag, Stephan J. Pankratz, Matthew B. Johnson, William F. Edmonds
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Patent number: 11562782Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.Type: GrantFiled: July 30, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventor: Adam D. Johnson
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Patent number: 11244733Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.Type: GrantFiled: November 15, 2019Date of Patent: February 8, 2022Assignee: Micron Technology, Inc.Inventors: Daniele Vimercati, Mark Fischer, Adam D. Johnson
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Publication number: 20200357456Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Inventor: Adam D. Johnson
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Patent number: 10770125Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.Type: GrantFiled: January 25, 2017Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventor: Adam D. Johnson
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Patent number: 10699784Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: GrantFiled: August 7, 2018Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Publication number: 20200090768Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.Type: ApplicationFiled: November 15, 2019Publication date: March 19, 2020Inventors: Daniele Vimercati, Mark Fischer, Adam D. Johnson
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Patent number: 10510423Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.Type: GrantFiled: August 4, 2017Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Daniele Vimercati, Mark Fischer, Adam D. Johnson
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Patent number: 10510773Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.Type: GrantFiled: August 28, 2017Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Adam D. Johnson
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Publication number: 20190043595Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.Type: ApplicationFiled: August 4, 2017Publication date: February 7, 2019Inventors: Daniele Vimercati, Mark Fischer, Adam D. Johnson
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Publication number: 20180342294Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Patent number: 10062432Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: GrantFiled: May 21, 2015Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Publication number: 20170358599Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.Type: ApplicationFiled: August 28, 2017Publication date: December 14, 2017Inventors: D.V. Nirmal Ramaswamy, Adam D. Johnson
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Patent number: 9786684Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.Type: GrantFiled: December 15, 2016Date of Patent: October 10, 2017Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Adam D. Johnson
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Patent number: 9779806Abstract: Resistive memory sensing methods and devices are described. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes.Type: GrantFiled: July 9, 2013Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventor: Adam D. Johnson
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Publication number: 20170133076Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Inventor: Adam D. Johnson
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Publication number: 20170098660Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: D.V. Nirmal Ramaswamy, Adam D. Johnson
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Patent number: 9558803Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.Type: GrantFiled: August 4, 2014Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventor: Adam D. Johnson