Abstract: A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Abstract: A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Abstract: A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.

Abstract: A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.

Abstract: Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.

Abstract: Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A chemical-mechanical polishing (CMP) pad conditioner. The conditioner has a non-uniform conditioning surface with a plurality of conditioning elements. The non-uniform surface comprises a first section having a first cutting volume per unit width and a second section having a second cutting volume per unit width that is different from the first cutting volume per unit width. The difference in cutting volume may be provided by different projected widths of the individual conditioning elements, by a difference in the linear density between the two sections, or by a difference in the cutting depth. A CMP tool comprising a polishing pad, a conditioning pad having the disclosed structure, and a mechanism for moving the polishing pad relative to the pad conditioner is also provided. A method is further provided for uniformly conditioning a CMP pad using a conditioner having the structure described.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A chemical-mechanical polishing (CMP) control system controls distribution of pressure across the backside of a semiconductor wafer being polished. The system includes a CMP apparatus having a carrier for supporting a semiconductor wafer. The carrier includes a plurality of dual function piezoelectric actuators. The actuators sense pressure variations across the semiconductor wafer and are individually controllable. A control is connected to the actuators for monitoring sensed pressure variations and controlling the actuators to provide a controlled pressure distribution across the semiconductor wafer.

Abstract: An in-situ method for regenerating a chemical-mechanical polishing pad which includes the steps of: forming the polishing pad by dispensing liquid moldable material, such as wax, polymers or water, on a polishing surface and solidifying the liquid material by reducing the temperature, allowing the moldable material to harden; distributing slurry material on the polishing pad; polishing the surface of a semiconductor wafer with a combination of the slurry material and the polishing pad; and regenerating in-situ the polishing pad. This method quickly, easily and repeatably, resurfaces and refreshes the surface on which the a semiconductor wafer is polished. The polishing pad may also include abrasives embedded therein to enhance its polishing capabilities.

Abstract: A wafer polishing fixture is disclosed containing a first liquid film confined by a non-porous but flexible enclosure for distributing evenly the applied polishing forces across the surface of a wafer supported by the confined liquid. The fixture comprises a flexible, non-porous template with a pocket for receiving a wafer to be polished. A washer is placed between a carrier and the template pocket. A film of water fills the bottom of the pocket and is confined with the aid of the washer and by an overlying porous pad extending across the pocket and having a non-porous sheath facing the liquid. A second liquid film saturates and covers the upper surface of the pad. The wafer to be polished floats upon the second liquid film within the pocket.