Abstract: An early fusion network is provided that reduces network load and enables easier design of specialized ASIC edge processors through performing a portion of convolutional neural network layers at distributed edge and data-network processors prior to transmitting data to a centralized processor for fully-connected/deconvolutional neural networking processing. Embodiments can provide convolution and downsampling layer processing in association with the digital signal processors associated with edge sensors. Once the raw data is reduced to smaller feature maps through the convolution-downsampling process, this reduced data is transmitted to a central processor for further processing such as regression, classification, and segmentation, along with feature combination of the data from the sensors.

Abstract: Various embodiments relate to a method for producing a plurality of weights for a neural network, wherein the neural network includes a plurality of layers, including: receiving a definition of the neural network including the number of layers and the size of the layers; and training the neural network using a training data set including: segmenting N weights of the plurality of weights into I weight sub-vectors {right arrow over (w)}(i) of dimension K=N/I; applying constraints that force sub-vectors {right arrow over (w)}(i) to concentrate near a (K?1)-dimensional single-valued hypersurface surrounding the origin; and quantizing sub-vectors {right arrow over (w)}(i) to a set of discrete K-dimensional quantization vectors {right arrow over (q)}(i) distributed in a regular pattern near the hypersurface, wherein each sub-vector {right arrow over (w)}(i) is mapped to its nearest quantization vector {right arrow over (q)}(i).

Abstract: A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.

Abstract: An early fusion network is provided that reduces network load and enables easier design of specialized ASIC edge processors through performing a portion of convolutional neural network layers at distributed edge and data-network processors prior to transmitting data to a centralized processor for fully-connected/deconvolutional neural networking processing. Embodiments can provide convolution and downsampling layer processing in association with the digital signal processors associated with edge sensors. Once the raw data is reduced to smaller feature maps through the convolution-downsampling process, this reduced data is transmitted to a central processor for further processing such as regression, classification, and segmentation, along with feature combination of the data from the sensors.

Abstract: Various exemplary embodiments relate to an event-driven processing unit (EPU) and a related method. A microprocessor may halt processing instructions when it executes a halting command. Thereafter, an EPU clock may stop its processing cycle and therefore halt microprocessor execution until it receives a start signal by a pattern detector. The pattern detector may use a plurality of bit slices to monitor a plurality of external inputs for the occurrence of events specified by the user. Some embodiments may also allow the user to check functioning by skipping upcoming instructions if a monitored event did not occur. By halting the EPU clock and the execution flow of the microprocessor, the event-driven microprocessor minimizes waste associated with executing a main control loop while waiting for a monitored event to occur. This may save processing capacity, memory, and power associated with continually running the main control loop.

Abstract: Embodiments of a method for operating an event-driven processor and an event-driven processor are described. In one embodiment, a method for operating an event-driven processor involves configuring a heartbeat timer of the event-driven processor and handling an event using the event-driven processor based on the heartbeat timer. Using a heartbeat timer built into the event-driven processor, the task execution determinism of the event-driven processor is improved and the power consumption of the event-driven processor is reduced. Other embodiments are also described.

Abstract: Embodiments of a method for operating an event-driven processor and an event-driven processor are described. In one embodiment, a method for operating an event-driven processor involves configuring a heartbeat timer of the event-driven processor and handling an event using the event-driven processor based on the heartbeat timer. Using a heartbeat timer built into the event-driven processor, the task execution determinism of the event-driven processor is improved and the power consumption of the event-driven processor is reduced. Other embodiments are also described.

Abstract: System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

Abstract: System and method for allocating memory resources are disclosed. The system utilizes a bus system coupled to a plurality of requestors and a plurality of memory systems coupled to the bus system. Each memory system includes a memory component and a memory management module including a value that represents access rights to the memory component. The memory management module is configured to receive an access request from a first requestor of the plurality of requestors and to grant access to the memory component only if the value indicates that the first requestor has access rights to the memory component. The memory management module is configurable to change the value to give the access rights to the memory component to a second requestor of the plurality of requestors.

Abstract: Various exemplary embodiments relate to an event-driven microprocessor and a related method. A microprocessor may halt processing instructions when it executes a halting command. Thereafter, an EPU clock may stop its processing cycle and therefore halt microprocessor execution until it receives a start signal by a pattern detector. The pattern detector may use a plurality of bit slices to monitor a plurality of external inputs for the occurrence of events specified by the user. Some embodiments may also allow the user to check functioning by skipping upcoming instructions if a monitored event did not occur. By halting the EPU clock and the execution flow of the microprocessor, the event-driven microprocessor minimizes waste associated with executing a main control loop while waiting for a monitored event to occur. This may save processing capacity, memory, and power associated with continually running the main control loop.

Abstract: A system and method for controlling an IC in different operational modes involves automatically loading operational configurations of target circuitries in the IC for a determined operational mode into at least one register and operating the target circuitries in the IC according to the operational configurations that are automatically loaded into the at least one register.

Abstract: A system and method for controlling an IC in different operational modes involves automatically loading operational configurations of target circuitries in the IC for a determined operational mode into at least one register and operating the target circuitries in the IC according to the operational configurations that are automatically loaded into the at least one register.

Abstract: A method of asynchronously transferring data from a low speed bus to a high speed bus, comprises latching data at a first predetermined instant in a cycle of the clock frequency of the high speed bus, latching data at a second predetermined instant in the same cycle of the clock frequency of the high speed bus, a time period between the second and first predetermined instants being less than the period of the data, and either, if the values of the latched data at the first and second predetermined instants are equal, the latched data is transferred at a third predetermined instant onto the high speed bus, or, if the values sampled at the first and second predetermined instants are different, at the third predetermined instant, transferring the value of the currently present data is transferred onto the high speed bus.

Abstract: A method of asynchronously transferring data from a low speed bus to a high speed bus, comprises latching data at a first predetermined instant in a cycle of the clock frequency of the high speed bus, latching data at a second predetermined instant in the same cycle of the clock frequency of the high speed bus, a time period between the second and first predetermined instants being less than the period of the data, and either, if the values of the latched data at the first and second predetermined instants are equal, the latched data is transferred at a third predetermined instant onto the high speed bus, or, if the values sampled at the first and second predetermined instants are different, at the third predetermined instant, transferring the value of the currently present data is transferred onto the high speed bus.