Abstract: An intra-picture prediction processor includes a first stage processing block to process incoming video data to identify intermediate intra-picture prediction information including a best intra-picture prediction angle and a best intra-picture block size. A second stage processing block operating on reconstructed blocks of video data selects final intra-picture prediction information for the reconstructed blocks of video data based upon the best intra-picture prediction angle and the best intra-picture block size.

Abstract: A graphics rendering system creates an image based on objects constructed of polygonal primitives, which can generate the perception of three-dimensional objects displayed on a two-dimensional display device. An anti-aliasing operation is applied to silhouette edges of the objects, which are the edges of primitives which are displayed at the perimeter of an object. A silhouette edge can be identified by determining how many times an edge is rendered, with each instance of the rendering of an edge corresponding to the rendering of a primitive that adjoins the edge. An edge that is rendered exactly once is interpreted as a silhouette edge. An example of a silhouette edge is an edge that adjoins one triangular primitive that is viewable and another triangular primitive that is hidden from view by other primitives.

Abstract: A method and system for simulating motion of a polygon on a display screen. The polygon may be included in a set of polygons used to model a three-dimensional object. The position of the polygon is defined by vertices tracked in a subpixel coordinate system existing in a computer-readable medium. The subpixel coordinates of the vertices are used to identify the pixels on the display screen having coordinates that correspond to subpixel coordinates lying within or, optionally, at the boundary of the polygon. The identified pixels are those that are to be lighted on the display screen to generate the image of the polygon. The display properties of the lighted pixels are selected by interpolation based on defined pixel display parameters assigned to the vertices of the triangle. As motion of the polygon is tracked in the subpixel coordinate system, the corresponding display on the display screen is repeatedly adjusted.

Abstract: Performing graphics rendering without the computational expense of hither plane clipping and with only a minimum of display image clipping. Where a three dimensional polygon crosses to both sides of a hither plane, any vertices on the back side of the hither plane are translated to the hither plane, producing polygons which occupy only the area in front of the hither plane. A display image memory, from which display images are generated, is located within a larger guard memory such that many images which would need to be clipped to fit in the display image memory may be written to the guard memory without clipping.

Abstract: A graphics rendering system creates an image based on objects constructed of polygonal primitives. Aliasing effects in the image are reduced by applying an anti-aliasing scheme to the areas of the image representing silhouette edges of the objects. The silhouette edges are anti-aliased by creating anti-aliasing primitives which vary in opacity. These anti-aliasing primitives are joined to the silhouetted edges, and create a region in the image where the objects appear to blend into the background.

Abstract: A system and method of selecting a level of detail in a texture-mapping system. Pixels are processed in a zig-zag traversal pattern to allow determination of vertical and horizontal change values in texture map coordinates. In this manner, accurate level of detail selection is achieved without unduly reducing efficiency or throughput of the graphics system.

Abstract: A system and method of rendering polygons in graphics system using incremental iterative addition in place of complex division operations. A setup engine provides relevant values to edge and span walk modules for rapid processing and rendering of polygon characteristics including material values. Characteristic functions are iterated with respect to polygon area and along individual spans to derive values for each pixel therein.

Abstract: An apparatus and method for enabling a cache controller and address and data buses of a microprocessor with an on-board cache to provide a SRAM test mode for testing the on-board cache. Upon assertion of a SRAM test signal to a SRAM test pin on the microprocessor chip, the cache and bus controllers cease normal functionality and permit data to be written to, and read from, individual addresses within the on-board cache as though the on-board cache is simple SRAM. After the chip is reset, standard SRAM tests can then be implemented by reading and writing data to selected cache memory addresses as though the cache memory were SRAM. Upon completion of the tests, the SRAM test signal is deasserted and the cache and bus controllers resume normal operating functionality. A reset signal is then applied to the microprocessor to reinitialize control logic employed within the microprocessor.

Abstract: A method and apparatus for maintaining cache coherency in a multiprocessor system having a plurality of processors and a shared main memory. Each of the plurality of processors is coupled to at least one cache unit and a store buffer. The method comprises the steps of writing by a first cache unit to its first store buffer a dirty line when the first cache unit experiences a cache miss; gaining control of the bus by the first cache unit; reading a new line from the share main memory by the first cache unit through the bus; writing the dirty line to the shared main memory if the bus is available to the first cache unit and if not available, the first cache unit checking snooping by a second cache unit from a second processor; comparing an address from the second cache unit with the tag of the dirty line, wherein the tag is stored in content-addressable memory coupled to the store buffer and if there is a hit, then supplying the dirty line to the second cache unit for updating.

Abstract: Two independently accessible subdivided cache tag arrays and a cache control logic is provided to a set associative cache system. Each tag entry is stored in two subdivided cache tag arrays, a physical and a set tag array such that each physical tag array entry has a corresponding set tag array entry. Each physical tag array entry stores the tag addresses and control bits for a set of cache lines. The control bits comprise at least one validity bit indicating whether the data stored in the corresponding cache line is valid. Each set tag array entry stores the descriptive bits for a set of cache lines which consists of the most recently used (MRU) field identifying the most recently used cache lines of the cache set. Each subdivided tag array is provided with its own interface to enable each array to be accessed concurrently but independently by the cache control logic which performs read and write operations against the cache.

Abstract: An apparatus and method for controlling the initialization of shifting circuitry which provides column redundancy for multiple banks of cache memory on-board a microprocessor. Upon sensing deassertion of a reset signal, a master controller supplies non-overlapping two phase clock signals to one bank controller for each bank of the cache memory. Each bank has a set of fuses which supply a bank shift location to the bank controller indicating the location of a bad column in the bank. The master controller also activates a pre-loadable counter which provides each bank controller with a signal which counts down to zero from half the maximum number of columns in a bank. Each bank controller then provides the shifting signals necessary to initialize the shifting circuitry for its bank. In this way, defective columns located in different positions in each bank can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.

Abstract: A caching arrangement which can work efficiently in a superscaler and multiprocessing environment includes separate caches for instructions and data and a single translation lookaside buffer (TLB) shared by them. During each clock cycle, retrievals from both the instruction cache and data cache may be performed, one on the rising edge of the clock cycle and one on the falling edge. The TLB is capable of translating two addresses per clock cycle. Because the TLB is faster than accessing the tag arrays which in turn are faster than addressing the cache data arrays, virtual addresses may be concurrently supplied to all three components and the retrieval made in one phase of a clock cycle. When an instruction retrieval is being performed, snooping for snoop broadcasts may be performed for the data cache and vice versa. Thus, for every clock cycle, an instruction and data cache retrieval may be performed as well as snooping.

Abstract: In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit.

Abstract: A cache array, a cache tag and comparator unit and a cache multiplexor are provided to a cache memory. Each cache operation performed against the cache array, read or write, takes only half a clock cycle. The cache tag and comparator unit comprises a cache tag array, a cache miss buffer and control logic. Each cache operation performed against the cache tag array, read or write, also takes only half a clock cycle. The cache miss buffer comprises cache miss descriptive information identifying the current state of a cache fill in progress. The control logic comprises a plurality of combinatorial logics for performing tag match operations. In addition to standard tag match operations, the control logic also conditionally tag matches an accessing address against an address tag stored in the cache miss buffer.