Abstract: The disclosed simulation environment, methods, and system support simultaneous design and analysis of assemblies with unified computer aided design (CAD) and finite element analysis (FEA). The system provides a simulation environment that is unified with the architecture of the assembly environment, which significantly reduces the amount of time it takes to set up structural simulations as compared to prior simulation tools. The system enables CAD designers to obtain accurate mechanical guidance such as strength and rigidity early and often in the design process, seeing the structural impact of CAD modifications at the sketch, part, and configuration level. Such guidance can be particularly helpful when CAD engineers are determining product fit and form, defining dimensions, and shaping the overall weight and volume of designs.

Abstract: A surface cleaning head includes a housing having a front side and back side, a brush roll rotatably mounted to the housing within a suction conduit and having at least a portion proximate the opening of the suction conduit, a leading roller mounted to the housing in front of the brush roll, and a drive mechanism operatively coupled to the brush roll and the leading roller for driving the brush roll and the leading roller at same time. The brush roll includes an agitator body and a first bristle/flap arrangement comprising a first deformable flap extending from the agitator body and a first bristle strip and/or row of tufts extending from the agitator body and disposed adjacent to the first deformable flap. The first deformable flap is disposed at an aggressive angle and the first bristle strip and/or row of tufts is arranged at a passive angle.

Abstract: A robotic cleaner includes a housing, a suction conduit with an opening, and a leading roller mounted in front of a brush roll. An inter-roller air passageway may be defined between the leading roller and the brush roll wherein the lower portion of the leading roller is exposed to a flow path to the suction conduit and an upper portion of the leading roller is outside of the flow path. Optionally, a combing unit includes a plurality of combing protrusions extending into the leading roller and having leading edges not aligned with a center of the leading roller. Optionally, a sealing strip is located along a rear side of the opening and along a portion of left and right sides of the opening. The underside may define side edge vacuum passageways extending from the sides of the housing partially between the leading roller and the sealing strip towards the opening.

Abstract: A vehicle wheel alignment system has a plurality of cameras, each camera for viewing a respective target disposed at a respective wheel of the vehicle and capturing image data of the target as the wheel and target are continuously rotated a number of degrees of rotation without a pause. The image data is used to calculate a minimum number of poses of the target of at least one pose for every five degrees of rotation as the wheel and target are continuously rotated the number of degrees of rotation without a pause. At least one of the cameras comprises a data processor for performing the steps of preprocessing the image data, and calculating an alignment parameter for the vehicle based on the preprocessed image data.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device including first and second semiconductor dies arranged on respective and first and second carriers, the first and second semiconductor dies each comprising a first contact and a second contact arranged on a top major surface of the respective semiconductor dies and a third contact arranged on a bottom major surface the respective semiconductor dies; first and second die connection portions, arranged on the respective first and second carriers, connected to the third contacts of the respective first and second semiconductor dies; and a first contact connection member, extending from the first contact of the first semiconductor die to the die connection portion of second carrier, electrical connection of the first contact of the first semiconductor die to the third contact of the second semiconductor die.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device including first and second semiconductor dies arranged on respective and first and second carriers, the first and second semiconductor dies each comprising a first contact and a second contact arranged on a top major surface of the respective semiconductor dies and a third contact arranged on a bottom major surface the respective semiconductor dies; first and second die connection portions, arranged on the respective first and second carriers, connected to the third contacts of the respective first and second semiconductor dies; and a first contact connection member, extending from the first contact of the first semiconductor die to the die connection portion of second carrier, electrical connection of the first contact of the first semiconductor die to the third contact of the second semiconductor die.

Abstract: A household appliance for treating at least one item according to at least one cycle of operation, includes a treating chamber with an access opening, a cover, and lock mechanism to secure the cover closed over the access opening. The lock mechanism is configured to allow the cover to be forced open without breaking the lock mechanism.

Abstract: A household appliance for treating at least one item according to at least one cycle of operation, includes a treating chamber with an access opening, a cover, and lock mechanism to secure the cover closed over the access opening. The lock mechanism is configured to allow the cover to be forced open without breaking the lock mechanism.

Abstract: The invention relates to FETs with stripe cells (6). Some of the cells have alternating low and high threshold regions (10, 8) along their length. In a linear operations regime, the low threshold regions conduct preferentially and increase the current density, thereby reducing the risk of thermal runaway. By distributing the low threshold regions (10) along the length of the cells (6), the risk of current crowding is reduced.

Abstract: A semiconductor device has a first region (10) and a second region (20), gate trenches (50) being formed in paid first and second regions including insulated gates to control conduction between source regions (42) and a common drain region (40) through a body region separated into first (34) and second (36) body regions. Isolation between the first and second regions is provided in a simple way by providing a gap between the first and second body regions (34,36) formed by eg. at least one trench (52) or a part of the drain region.

Abstract: The invention relates to FETs with stripe cells (6). Some of the cells have alternating low and high threshold regions (10, 8) along their length. In a linear operations regime, the low threshold regions conduct preferentially and increase the current density, thereby reducing the risk of thermal runaway. By distributing the low threshold regions (10) along the length of the cells (6), the risk of current crowding is reduced.

Abstract: The present invention provides for a MOSFET device (10) having a body diode structure (22) and provided with biasing means arranged to provide a bias voltage selectively applied to the gate of the MOSFET (12) during reverse recovery of the body diode structure (22) so as to reduce reverse recovery transient signals associated with the body diode structure (22), the biasing means comprising a diode device (16) located in the gate path of the device (10).

Abstract: A trench-gate MOSFET or ACCUFET has its gate (21) in a first trench (20) that extends through a channel-accommodating body region (15) to a drain region (14). Within the transistor cells, a second trench (40) comprising deposited highly-doped semiconductor material (41) extends to the drain region (14). This highly-doped material (41) is of opposite conductivity type to the drain region (14) and, together with a possible out-diffusion profile (42), forms a localized region (41, 42) that is separated from the first trench (20) by the body region 15. A source electrode (23) contacts the source region (13) and the whole top area of the localized region (41, 42). In a MOSFET, the localized region (41, 42) provides protection against turning on of the cell's parasitic bipolar transistor. In an ACCUFET (FIG. 9), the localized region (41, 42) depletes the channel-accommodating body region (15A).

Abstract: The invention relates to a write-once read-many memory element (1), or an assembly thereof, which comprises a substrate on which electrodes are provided and between which a layer is sandwiched, which memory element includes a conjugated polymer or oligomer as well as a dopant. This memory element can be written by temporarily applying a sufficiently high voltage to the electrodes so that the electroconductivity of the layer is permanently reduced.

Abstract: The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2).

Abstract: A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3.

Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly.

Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4).

Abstract: A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

Abstract: A trench gate field effect device has a semiconductor body (2) with a trench (3) extending into a first major surface (2a) so as to define a regular array of polygonal source cells (4). Each source cell contains a source region (5a,5b) and a body region (6a,6b) with the body regions separating the source regions from a common further region (20). A gate (G) extends within and along said trench (3) for controlling a conduction channel through each of the body regions. Each source cell (4) has a central semiconductor region (60) which is more highly doped than said body regions, is of opposite conductivity type to the further region and forms a diode with the further region. Each source cell (4) has an inner trench boundary (3a) and an outer polygonal trench boundary (3b) with the inner trench boundary bounding a central subsidiary cell (10a) containing the central semiconductor region (60).