Abstract: A method of sampling instructions executing in a multi-threaded processor which includes selecting an instruction for sampling, storing information relating to the instruction, determining whether the instruction includes an event of interest, and reporting the instruction if the instruction includes an event of interest on a per-thread basis. The event of interest includes information relating to a thread to which the instruction is bound.

Abstract: A system and method for profiling runtime system events of a computer system may include associating a data source type with detected system events. The system events may be detected dependent on information included in a reply message received by a processor in response to a data request or other transaction request message. The reply message may include information characterizing a source type of a source of data included in the reply message. The source type information may indicate that the source is remote or local; that it is a shared or a private storage location; that the data is supplied via a cache-to-cache transfer; or that the data is sourced from a coherency domain other than that of the requesting process. Instructions, events, messages, and replies may be sampled, and extended address information corresponding to the samples may be stored in an event set database for performance analysis.

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.

Abstract: Associating data source information with sampled runtime events allows identification of system components related to the sampled runtime events. Code can be optimized from the perspective of system components and for various architectures. A system provides a data source indication. The system associates the data source indication with a corresponding instruction instance. The instruction instance is related to a sampled runtime event, and the sampled runtime event is associated with the data source indication. The data source information and associated sampled runtime event can be supplied for profiling code.

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.

Abstract: In one embodiment, a processor comprises a core configured to execute instructions; a register file comprising a plurality of storage locations; and a window management unit. The window management unit is configured to operate the plurality of storage locations as a plurality of windows, wherein register addresses encoded into the instructions identify storage locations among a subset of the plurality of storage locations that are within a current window. Additionally, the window management unit is configured to allocate a second window in response to a predetermined event. One of the current window and the second window serves as a checkpoint of register state, and the other one of the current window and the second window is updated in response to instructions processed subsequent to the checkpoint. The checkpoint may be restored if the speculative execution results are discarded.

Abstract: A method and apparatus of improving prediction accuracy of a branch instruction scheme includes reading an individual instruction in a current set of instructions, fetching the individual instruction when an instruction fetch unit determines that the individual instruction is valid, and allowing the instruction fetch unit to use an index address for the fetched individual instruction. A method and apparatus of improving branch prediction accuracy includes receiving a set of instructions having an assigned address, making a prediction for a branch instruction in the set of instructions using the assigned address, and retaining the assigned address for the branch instruction in the set of instructions.

Abstract: One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

Abstract: A method for improving prediction of an outcome for a branch instruction in a set of instructions includes storing local branch history data for the branch instruction, using the local branch history data to predict the outcome of the branch instruction, and speculatively updating the local branch history data with the predicted outcome of the branch instruction. An apparatus for improving prediction of an outcome for a branch instruction in a set of instructions includes a memory for storing local branch history data for the branch instruction and a processor for using the local branch history data to predict the outcome of the branch instruction and speculatively updating the local branch history data with the predicted outcome of the branch instruction.

Abstract: One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

Abstract: A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set, and based on a class of the exception, processing the exception differently before signaling the trap. The method may include replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception. The method may include replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction. The method may include signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction. The method may include marking an instruction causing the exception as complete without issuing the instruction causing the exception.

Abstract: A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

Abstract: A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

Abstract: A method and apparatus for performing multiple branch predictions per cycle is disclosed. The method and apparatus according to the present invention determine, within one fetch cycle, which instructions in a plurality of fetch instructions are branches and whether such branches are taken or not taken thereby finding the oldest taken branch, which has a target address that is fetched within the same fetch cycle.

Abstract: A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

Abstract: A method for repairing a pipeline in response to a branch instruction having a branch, includes the steps of providing a branch repair table having a plurality of entries, allocating an entry in the branch repair table for the branch instruction, storing a target address, a fall-through address, and repair information in the entry in the branch repair table, processing the branch instruction to determine whether the branch was taken, and repairing the pipeline in response to the repair information and the fall-through address in the entry in the branch repair table when the branch was not taken.

Abstract: Two-way set associative data is stored in a cache memory array. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.

Abstract: One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction stream. This system concurrently performs a fast single-cycle branch prediction operation to produce a first predicted address, and a more-accurate multiple-cycle branch prediction operation to produce a second predicted address. The system assumes that the first predicted address is correct and proceeds with a subsequent instruction fetch operation using the first predicted address. If the first predicted address is the same as the second predicted address, the subsequent instruction fetch operation is allowed to proceed using the first predicted address. Otherwise, the subsequent fetch operation is delayed so that it can proceed using the second predicted address.