Patents by Inventor Adarsh BASAVALINGAPPA
Adarsh BASAVALINGAPPA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955494Abstract: An imaging device includes a first pixel including a first photoelectric conversion region and a first amplification transistor, a second pixel adjacent the first pixel and including a second photoelectric conversion region and a second amplification transistor, and a first contact coupled to the first amplification transistor and the second amplification transistor, and that receives a power supply signal for the first amplification transistor and the second amplification transistor.Type: GrantFiled: May 21, 2020Date of Patent: April 9, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Adarsh Basavalingappa, Taisuke Suwa, Michiel Timmermans, Frederick Brady, Jeongsoo Han
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Publication number: 20230030282Abstract: A sensor chip including a resistor and a backside illuminated single photon avalanche diode (SPAD) that is connected to the resistor; and a sensor including a sensor chip with a resistor and a backside illuminated SPAD that is connected to the resistor. The backside illuminated SPAD including an anode, a cathode, and a multiplication structure.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Adarsh Basavalingappa, Cristian Tivarus, Sungin Hwang, Yoshiaki Tashiro
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Publication number: 20220254821Abstract: An imaging device includes a first pixel #1 including a first photoelectric conversion region and a first amplification transistor AMPO, a second pixel #2 adjacent the first pixel #1 and including a second photoelectric conversion region and a second amplification transistor AMP1, and a first contact C1 coupled to the first amplification transistor AMPO and the second amplification transistor AMP1, and that receives a power supply signal VDD for the first amplification transistor and the second amplification transistor. That is, neighboring pixels in a same row share a VDD contact. A wiring may connect the VDD nodes of amplification transistors AMP for an entire row of pixels. Reset transistors RSTO and RST1, and overflow transistors OFG of each pixel #1 and #2 may be connected to a same power supply. This power supply may be the same or different from the power supply VDD.Type: ApplicationFiled: May 21, 2020Publication date: August 11, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Adarsh BASAVALINGAPPA, Taisuke SUWA, Michiel TIMMERMANS, Frederick BRADY, Jeongsoo HAN
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Publication number: 20220247952Abstract: A pixel array includes a plurality of pixels. Each pixel includes a photoelectric conversion region that converts incident light into electric charge, and a charge transfer section coupled to the photoelectric conversion region and having line symmetry along a first axis in a plan view. The charge transfer section includes a first transfer transistor coupled to a first floating diffusion and the photoelectric conversion region and located at a first side of the photoelectric conversion region, and a second transfer transistor coupled to a second floating diffusion and the photoelectric conversion region and located at the first side of the photoelectric conversion region.Type: ApplicationFiled: May 21, 2020Publication date: August 4, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Frederick BRADY, Adarsh BASAVALINGAPPA, Taisuke SUWA, Michiel TIMMERMANS, Sungin HWANG
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Publication number: 20220238577Abstract: An imaging device includes a first pixel. The first pixel includes a first photoelectric conversion region, and first, second, third, and fourth transistors coupled to the first photoelectric conversion region and that transfer charge from the first photoelectric conversion region. In a plan view, gates of the first, second, third, and fourth transistors are arranged at a periphery of the first photoelectric conversion region in a first symmetrical pattern.Type: ApplicationFiled: May 21, 2020Publication date: July 28, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Adarsh BASAVALINGAPPA, Frederick BRADY
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Publication number: 20220217289Abstract: An imaging device includes a first pixel. The first pixel includes a first photoelectric conversion region, and first and second transistors coupled to the first photoelectric conversion region to transfer charge generated by the first photoelectric conversion region. The imaging device includes a first driving circuit and a second driving circuit to drive the first pixel in a first mode and a second mode, the first mode being a mode in which the first driving circuit applies a first set of transfer signals to the first and second transfer transistors, the second mode being a mode in which the second driving circuit applies a transfer signal to only one of the first and second transfer transistors.Type: ApplicationFiled: May 21, 2020Publication date: July 7, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Sungin HWANG, Frederick BRADY, Adarsh BASAVALINGAPPA, Taisuke SUWA, Michiel TIMMERMANS
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Publication number: 20220216253Abstract: An imaging device includes a pixel including a photoelectric conversion region, a first transfer transistor coupled to the photoelectric conversion region, a first floating diffusion, a second floating diffusion, a second transfer transistor coupled between the first floating diffusion and the second floating diffusion to control access to the second floating diffusion, a third transfer transistor coupled to the photoelectric conversion region, a third floating diffusion coupled, a fourth floating diffusion, and a fourth transfer transistor coupled between the third floating diffusion and the fourth floating diffusion to control access to the fourth floating diffusion. The imaging device includes a first wiring layer including a first wiring connected to the second floating diffusion, a second wiring connected to the fourth floating diffusion, and a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring.Type: ApplicationFiled: May 21, 2020Publication date: July 7, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Frederick BRADY, Adarsh BASAVALINGAPPA, Taisuke SUWA, Michiel TIMMERMANS, Sungin HWANG
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Patent number: 10541141Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: GrantFiled: July 25, 2018Date of Patent: January 21, 2020Assignee: Lam Research CorporationInventors: Adarsh Basavalingappa, Peng Wang, Bhaskar Nagabhirava, Michael Goss, Prabhakara Gopaladasu, Randolph Knarr, Stefan Schmitz, Phil Friddle
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Publication number: 20180330959Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: ApplicationFiled: July 25, 2018Publication date: November 15, 2018Inventors: Adarsh BASAVALINGAPPA, Peng WANG, Bhaskar NAGABHIRAVA, Michael GOSS, Prabhakara GOPALADASU, Randolph KNARR, Stefan SCHMITZ, Phil FRIDDLE
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Patent number: 10037890Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: GrantFiled: October 11, 2016Date of Patent: July 31, 2018Assignee: Lam Research CorporationInventors: Adarsh Basavalingappa, Peng Wang, Bhaskar Nagabhirava, Michael Goss, Prabhakara Gopaladasu, Randolph Knarr, Stefan Schmitz, Phil Friddle
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Patent number: 10002773Abstract: A method for selectively etching trenches in a silicon oxide containing layer with an organic planarization layer is provided. Processing the silicon oxide layer comprises a plurality of process cycles, wherein each etch cycle comprises a deposition phase, comprising providing a flow of a deposition phase gas comprising a fluorocarbon or hydrofluorocarbon containing gas with a fluorine to carbon ratio, providing a constant RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase and an etch phase, comprising providing a flow of an etch phase gas comprising a fluorocarbon or hydrofluorocarbon containing gas with a fluorine to carbon ratio that is higher than the fluorine to carbon ratio of the deposition phase gas, providing a pulsed RF power, which forms the etch phase gas into a plasma, and stopping the etch phase.Type: GrantFiled: October 11, 2016Date of Patent: June 19, 2018Assignee: Lam Research CorporationInventors: Bhaskar Nagabhirava, Adarsh Basavalingappa, Peng Wang, Prabhakara Gopaladasu, Michael Goss
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Publication number: 20180102253Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Inventors: Adarsh BASAVALINGAPPA, Peng WANG, Bhaskar NAGABHIRAVA, Michael GOSS, Prabhakara GOPALADASU, Randolph KNARR, Stefan SCHMITZ, Phil FRIDDLE
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Publication number: 20180102257Abstract: A method for selectively etching trenches in a silicon oxide containing layer with an organic planarization layer is provided. Processing the silicon oxide layer comprises a plurality of process cycles, wherein each etch cycle comprises a deposition phase, comprising providing a flow of a deposition phase gas comprising a fluorocarbon or hydrofluorocarbon containing gas with a fluorine to carbon ratio, providing a constant RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase and an etch phase, comprising providing a flow of an etch phase gas comprising a fluorocarbon or hydrofluorocarbon containing gas with a fluorine to carbon ratio that is higher than the fluorine to carbon ratio of the deposition phase gas, providing a pulsed RF power, which forms the etch phase gas into a plasma, and stopping the etch phase.Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Inventors: Bhaskar NAGABHIRAVA, Adarsh BASAVALINGAPPA, Peng WANG, Prabhakara GOPALADASU, Michael Goss