Abstract: A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage device is adapted to output a plurality of data blocks in parallel. A data bus provides a data path wide enough to accommodate the parallel data blocks and is further coupled to a plurality of CRC cores coupled to the data bus, wherein CRC values are calculated for every combination of data blocks on the data bus. A multiplexer coupled to the CRC cores selects the output of one of the CRC cores based on the number of valid data blocks on the data bus. Once the correct CRC value has been calculated, it is appended to a data segment, comprised of a group of data blocks, for transmission to another device.

Abstract: A system and method are provided for inserting Interval Markers in a data stream comprising data blocks. Included is a Buffer having a predetermined number of registers for temporarily and storing data blocks read from a Target System, wherein the Buffer temporarily stores a portion of a data transmission requested from an Initiator System. A Block Counter indicates the number of data blocks in the data stream that have been read into the Buffer. A Marker Offset counter indicates where an Interval Marker are inserted relative to the data blocks in the data stream. A Data Transmitter transmits the data blocks temporarily stored within the Buffer whenever sufficient data is present in the Buffer and Interval Markers have been inserted if required, wherein the Data Transmitter updates the Block Counter and the Marker Offset counter after the contents of the Buffer have been transferred to the Data Transmitter.

Abstract: A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage device is adapted to output a plurality of data blocks in parallel. A data bus provides a data path wide enough to accommodate the parallel data blocks and is further coupled to a plurality of CRC cores coupled to the data bus, wherein CRC values are calculated for every combination of data blocks on the data bus. A multiplexer coupled to the CRC cores selects the output of one of the CRC cores based on the number of valid data blocks on the data bus. Once the correct CRC value has been calculated, it is appended to a data segment, comprised of a group of data blocks, for transmission to another device.

Abstract: A system and method are provided for inserting Interval Markers in a data stream comprising data blocks. Included is a Buffer having a predetermined number of registers for temporarily and storing data blocks read from a Target System, wherein the Buffer temporarily stores a portion of a data transmission requested from an Initiator System. A Block Counter indicates the number of data blocks in the data stream that have been read into the Buffer. A Marker Offset counter indicates where an Interval Marker are inserted relative to the data blocks in the data stream. A Data Transmitter transmits the data blocks temporarily stored within the Buffer whenever sufficient data is present in the Buffer and Interval Markers have been inserted if required, wherein the Data Transmitter updates the Block Counter and the Marker Offset counter after the contents of the Buffer have been transferred to the Data Transmitter.

Abstract: A value of difference between exponent values and an inverted value thereof obtained by an inverting circuit are calculated using one subtractor and one of the value of the difference and the inverted value of the difference is selected in accordance with a signal indicating which of the exponent values is greater. Only one subtractor is used, so that the scale of the circuit is reduced and the reduction in chip real estate and power consumption can be achieved. Thus, a circuit for calculating an absolute value of difference between exponent values for right-shifting a floating-point number is provided, with reduced chip real estate and power consumption.

Abstract: A value of difference between exponent values and an inverted value thereof obtained by an inverting circuit are calculated using one subtractor and one of the value of the difference and the inverted value of the difference is selected in accordance with a signal indicating which of the exponent values is greater. Only one subtractor is used, so that the scale of the circuit is reduced and the reduction in chip real estate and power consumption can be achieved. Thus, a circuit for calculating an absolute value of difference between exponent values for right-shifting a floating-point number is provided, with reduced chip real estate and power consumption.