Patents by Inventor Addison Crockett

Addison Crockett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silicon-on-insulator substrate including trap-rich layer and methods for making thereof
    Patent number: 11894261
    Abstract: A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV?1 to 1.2*1010 cm2 eV?1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 6, 2024
    Inventor: Addison Crockett
  • SILICON-ON-INSULATOR SUBSTRATE INCLUDING TRAP-RICH LAYER AND METHODS FOR MAKING THEREOF
    Publication number: 20210407850
    Abstract: A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV?1 to 1.2*1010 cm2 eV?1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.
    Type: Application
    Filed: September 10, 2021
    Publication date: December 30, 2021
    Inventor: Addison Crockett
  • Silicon-on-insulator substrate including trap-rich layer and methods for making thereof
    Patent number: 11145537
    Abstract: A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV?1 to 1.2*1010 cm2 eV?1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: October 12, 2021
    Inventor: Addison Crockett
  • SILICON-ON-INSULATOR SUBSTRATE INCLUDING TRAP-RICH LAYER AND METHODS FOR MAKING THEREOF
    Publication number: 20210104430
    Abstract: A silicon-on-insulator substrate includes: (1) a high-resistivity base layer including silicon and a trap-rich region including arsenic diffused within a first side of the high-resistivity base layer, wherein the trap-rich region has a thickness that is in a range of 1 to 10 microns and a trap density that is in a range of 0.8*1010 cm2 eV?1 to 1.2*1010 cm2 eV?1, wherein the high-resistivity base layer has resistivity in a range of 50 to 100 ohm-meters and a thickness in a range of 500 to 700 microns; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness that is in a range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer, wherein the transfer layer comprises a silicon wafer having a thickness that is a range of 500 to 5000 angstroms.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 8, 2021
    Inventor: Addison Crockett